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scripts: allow macro preplacement
Signed-off-by: Arthur Koucher <[email protected]>
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8 files changed

+42
-39
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8 files changed

+42
-39
lines changed

‎docs/user/FlowVariables.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,6 @@ configuration file.
155155
| <a name="LIB_FILES"></a>LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| |
156156
| <a name="MACRO_BLOCKAGE_HALO"></a>MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| |
157157
| <a name="MACRO_EXTENSION"></a>MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| |
158-
| <a name="MACRO_PLACEMENT_TCL"></a>MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| |
159158
| <a name="MACRO_PLACE_HALO"></a>MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| |
160159
| <a name="MACRO_ROWS_HALO_X"></a>MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| |
161160
| <a name="MACRO_ROWS_HALO_Y"></a>MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| |
@@ -176,6 +175,7 @@ configuration file.
176175
| <a name="PLATFORM"></a>PLATFORM| Specifies process design kit or technology node to be used.| |
177176
| <a name="PLATFORM_TCL"></a>PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| |
178177
| <a name="POST_CTS_TCL"></a>POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| |
178+
| <a name="PREPLACE_MACROS_TCL"></a>PREPLACE_MACROS_TCL| Specifies the path of a TCL file on how to place macros manually before the macro placement stage. The use may choose to place just some of the macro in the design. In this case, the macro placer will handle the remaining unplaced macros.| |
179179
| <a name="PRE_GLOBAL_ROUTE_TCL"></a>PRE_GLOBAL_ROUTE_TCL| Specifies a Tcl script with commands to run before global route.| |
180180
| <a name="PROCESS"></a>PROCESS| Technology node or process in use.| |
181181
| <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| |
@@ -298,7 +298,6 @@ configuration file.
298298
- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
299299
- [IO_CONSTRAINTS](#IO_CONSTRAINTS)
300300
- [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO)
301-
- [MACRO_PLACEMENT_TCL](#MACRO_PLACEMENT_TCL)
302301
- [MACRO_PLACE_HALO](#MACRO_PLACE_HALO)
303302
- [MACRO_ROWS_HALO_X](#MACRO_ROWS_HALO_X)
304303
- [MACRO_ROWS_HALO_Y](#MACRO_ROWS_HALO_Y)
@@ -311,6 +310,7 @@ configuration file.
311310
- [PLACE_DENSITY](#PLACE_DENSITY)
312311
- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
313312
- [PLACE_SITE](#PLACE_SITE)
313+
- [PREPLACE_MACROS_TCL](#PREPLACE_MACROS_TCL)
314314
- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
315315
- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
316316
- [RTLMP_AREA_WT](#RTLMP_AREA_WT)

‎flow/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -411,7 +411,7 @@ $(eval $(call do-copy,2_floorplan,2_1_floorplan.sdc,,.sdc))
411411

412412
# STEP 2: Macro Placement
413413
#-------------------------------------------------------------------------------
414-
$(eval $(call do-step,2_2_floorplan_macro,$(RESULTS_DIR)/2_1_floorplan.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place))
414+
$(eval $(call do-step,2_2_floorplan_macro,$(RESULTS_DIR)/2_1_floorplan.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(PREPLACE_MACROS_TCL),macro_place))
415415

416416
# STEP 3: Tapcell and Welltie insertion
417417
#-------------------------------------------------------------------------------

‎flow/designs/asap7/mock-array/BUILD.bazel‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ orfs_flow(
135135
sources = {
136136
"SDC_FILE": [":mock-array-constraints"],
137137
"IO_CONSTRAINTS": [":mock-array-io"],
138-
# "MACRO_PLACEMENT_TCL": [":macro-placement.tcl"],
138+
# "PREPLACE_MACROS_TCL": [":macro-placement.tcl"],
139139
},
140140
verilog_files = ["//flow/designs/src/mock-array:verilog"],
141141
)

‎flow/designs/asap7/mock-array/config.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ export BLOCKS ?= Element
3636
ifneq ($(BLOCKS),)
3737
export GDS_ALLOW_EMPTY = Element
3838
ifneq ($(RTLMP_FLOW), 1)
39-
export MACRO_PLACEMENT_TCL = $(DESIGN_HOME)/asap7/mock-array/macro-placement.tcl
39+
export PREPLACE_MACROS_TCL = $(DESIGN_HOME)/asap7/mock-array/macro-placement.tcl
4040
endif
4141
export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl
4242
endif

‎flow/designs/sky130hd/chameleon/config.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ export ADDITIONAL_LEFS = $(chameleon_DIR)/lef/apb_sys_0.lef \
4444
$(chameleon_DIR)/lef/DMC_32x16HC.lef \
4545
$(chameleon_DIR)/lef/ibex_wrapper.lef
4646

47-
export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl
47+
export PREPLACE_MACROS_TCL = $(chameleon_DIR)/macro_placement.tcl
4848

4949
export FP_PDN_RAIL_WIDTH = 0.48
5050
export FP_PDN_RAIL_OFFSET = 0

‎flow/scripts/macro_place_util.tcl‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -34,42 +34,42 @@ if { [find_macros] != "" } {
3434
set blockage_width $::env(MACRO_BLOCKAGE_HALO)
3535
}
3636

37-
if { [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL] } {
38-
log_cmd source $::env(MACRO_PLACEMENT_TCL)
39-
} else {
40-
set additional_rtlmp_args ""
41-
append_env_var additional_rtlmp_args RTLMP_MAX_LEVEL -max_num_level 1
42-
append_env_var additional_rtlmp_args RTLMP_MAX_INST -max_num_inst 1
43-
append_env_var additional_rtlmp_args RTLMP_MIN_INST -min_num_inst 1
44-
append_env_var additional_rtlmp_args RTLMP_MAX_MACRO -max_num_macro 1
45-
append_env_var additional_rtlmp_args RTLMP_MIN_MACRO -min_num_macro 1
46-
append additional_rtlmp_args " -halo_width $halo_x"
47-
append additional_rtlmp_args " -halo_height $halo_y"
48-
append_env_var additional_rtlmp_args RTLMP_MIN_AR -min_ar 1
49-
append_env_var additional_rtlmp_args RTLMP_SIGNATURE_NET_THRESHOLD -signature_net_threshold 1
50-
append_env_var additional_rtlmp_args RTLMP_AREA_WT -area_weight 1
51-
append_env_var additional_rtlmp_args RTLMP_WIRELENGTH_WT -wirelength_weight 1
52-
append_env_var additional_rtlmp_args RTLMP_OUTLINE_WT -outline_weight 1
53-
append_env_var additional_rtlmp_args RTLMP_BOUNDARY_WT -boundary_weight 1
54-
append_env_var additional_rtlmp_args RTLMP_NOTCH_WT -notch_weight 1
55-
append_env_var additional_rtlmp_args RTLMP_DEAD_SPACE -target_dead_space 1
56-
append_env_var additional_rtlmp_args RTLMP_RPT_DIR -report_directory 1
57-
append_env_var additional_rtlmp_args RTLMP_FENCE_LX -fence_lx 1
58-
append_env_var additional_rtlmp_args RTLMP_FENCE_LY -fence_ly 1
59-
append_env_var additional_rtlmp_args RTLMP_FENCE_UX -fence_ux 1
60-
append_env_var additional_rtlmp_args RTLMP_FENCE_UY -fence_uy 1
37+
if { [env_var_exists_and_non_empty PREPLACE_MACROS_TCL] } {
38+
log_cmd source $::env(PREPLACE_MACROS_TCL)
39+
}
6140

62-
append additional_rtlmp_args " -target_util [place_density_with_lb_addon]"
41+
set additional_rtlmp_args ""
42+
append_env_var additional_rtlmp_args RTLMP_MAX_LEVEL -max_num_level 1
43+
append_env_var additional_rtlmp_args RTLMP_MAX_INST -max_num_inst 1
44+
append_env_var additional_rtlmp_args RTLMP_MIN_INST -min_num_inst 1
45+
append_env_var additional_rtlmp_args RTLMP_MAX_MACRO -max_num_macro 1
46+
append_env_var additional_rtlmp_args RTLMP_MIN_MACRO -min_num_macro 1
47+
append additional_rtlmp_args " -halo_width $halo_x"
48+
append additional_rtlmp_args " -halo_height $halo_y"
49+
append_env_var additional_rtlmp_args RTLMP_MIN_AR -min_ar 1
50+
append_env_var additional_rtlmp_args RTLMP_SIGNATURE_NET_THRESHOLD -signature_net_threshold 1
51+
append_env_var additional_rtlmp_args RTLMP_AREA_WT -area_weight 1
52+
append_env_var additional_rtlmp_args RTLMP_WIRELENGTH_WT -wirelength_weight 1
53+
append_env_var additional_rtlmp_args RTLMP_OUTLINE_WT -outline_weight 1
54+
append_env_var additional_rtlmp_args RTLMP_BOUNDARY_WT -boundary_weight 1
55+
append_env_var additional_rtlmp_args RTLMP_NOTCH_WT -notch_weight 1
56+
append_env_var additional_rtlmp_args RTLMP_DEAD_SPACE -target_dead_space 1
57+
append_env_var additional_rtlmp_args RTLMP_RPT_DIR -report_directory 1
58+
append_env_var additional_rtlmp_args RTLMP_FENCE_LX -fence_lx 1
59+
append_env_var additional_rtlmp_args RTLMP_FENCE_LY -fence_ly 1
60+
append_env_var additional_rtlmp_args RTLMP_FENCE_UX -fence_ux 1
61+
append_env_var additional_rtlmp_args RTLMP_FENCE_UY -fence_uy 1
6362

64-
set all_args $additional_rtlmp_args
63+
append additional_rtlmp_args " -target_util [place_density_with_lb_addon]"
6564

66-
if { [env_var_exists_and_non_empty RTLMP_ARGS] } {
67-
set all_args $::env(RTLMP_ARGS)
68-
}
65+
set all_args $additional_rtlmp_args
6966

70-
log_cmd rtl_macro_placer {*}$all_args
67+
if { [env_var_exists_and_non_empty RTLMP_ARGS] } {
68+
set all_args $::env(RTLMP_ARGS)
7169
}
7270

71+
log_cmd rtl_macro_placer {*}$all_args
72+
7373
source $::env(SCRIPTS_DIR)/placement_blockages.tcl
7474
block_channels $blockage_width
7575
} else {

‎flow/scripts/variables.yaml‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -341,9 +341,12 @@ TAPCELL_TCL:
341341
Path to Endcap and Welltie cells file.
342342
stages:
343343
- floorplan
344-
MACRO_PLACEMENT_TCL:
344+
PREPLACE_MACROS_TCL:
345345
description: |
346-
Specifies the path of a TCL file on how to place certain macros manually.
346+
Specifies the path of a TCL file on how to place macros manually before the
347+
macro placement stage. The use may choose to place just some of the macro in
348+
the design. In this case, the macro placer will handle the remaining unplaced
349+
macros.
347350
stages:
348351
- floorplan
349352
MACRO_PLACE_HALO:

‎flow/util/makeIssue.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ ISSUE_CP_DESIGN_FILE_VARS="SDC_FILE \
1717
FOOTPRINT \
1818
SIG_MAP_FILE \
1919
IO_CONSTRAINTS \
20-
MACRO_PLACEMENT_TCL \
20+
PREPLACE_MACROS_TCL \
2121
MACRO_WRAPPERS \
2222
RTLMP_CONFIG_FILE \
2323
DFF_LIB_FILE "

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