Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenROAD-flow-scripts into add_variables_repair_antennas_iter

Author: eder-matheus

docs/user/FlowVariables.md

@@ -233,6 +233,7 @@ configuration file.
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096|
 | <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0|
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
+| <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| List of modules to apply retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. This is an experimental option and may cause adverse effects.| |
 | <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| |
@@ -269,6 +270,7 @@ configuration file.
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
 - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE)
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
+- [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES)
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)

flow/scripts/abc_retime.script

@@ -0,0 +1,3 @@
+st
+retime -v -o
+map

flow/scripts/report_metrics.tcl

@@ -32,6 +32,11 @@ proc report_metrics { stage when { include_erc true } { include_clock_skew true
   report_worst_slack >> $filename
   report_worst_slack_metric
   report_worst_slack_metric -hold
+
+  report_puts "\n=========================================================================="
+  report_puts "$when report_clock_min_period"
+  report_puts "--------------------------------------------------------------------------"
+  report_clock_min_period -include_port_paths >> $filename
   report_fmax_metric
 
   if { $include_clock_skew && $::env(REPORT_CLOCK_SKEW) } {

flow/scripts/synth.tcl

@@ -56,6 +56,16 @@ json -o $::env(RESULTS_DIR)/mem.json
 exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \
   --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
 
+if { [env_var_exists_and_non_empty SYNTH_RETIME_MODULES] } {
+  select $::env(SYNTH_RETIME_MODULES)
+  opt -fast -full
+  memory_map
+  opt -full
+  techmap
+  abc -dff -script scripts/abc_retime.script
+  select -clear
+}
+
 if {
   [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
   [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]

flow/scripts/variables.yaml

@@ -200,6 +200,14 @@ SYNTH_CANONICALIZE_TCL:
     canonicalize step.
   stages:
     - synth
+SYNTH_RETIME_MODULES:
+  description: >
+    List of modules to apply retiming to. These modules must not get
+    dissolved and as such they should either be the top module or be included
+    in SYNTH_KEEP_MODULES. This is an experimental option and may cause adverse
+    effects.
+  stages:
+    - synth
 LATCH_MAP_FILE:
   description: |
     List of latches treated as a black box by Yosys.