synth: Factor out read procs from preamble

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/scripts/synth.tcl

@@ -1,6 +1,5 @@
-set ::env(RTLIL_FILE) $::env(RESULTS_DIR)/1_synth.rtlil
-
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
+read_checkpoint $::env(RESULTS_DIR)/1_synth.rtlil
 
 hierarchy -check -top $::env(DESIGN_NAME)
 

flow/scripts/synth_canonicalize.tcl

@@ -1,4 +1,5 @@
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
+read_design_sources
 
 dict for {key value} $::env(VERILOG_TOP_PARAMS) {
   # Apply toplevel parameters

flow/scripts/synth_preamble.tcl

@@ -21,16 +21,16 @@ if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} {
   exit
 }
 
-# Read design
-if {[env_var_exists_and_non_empty RTLIL_FILE]} {
+proc read_checkpoint {file} {
   # We are reading a Yosys checkpoint
-  set file $env(RTLIL_FILE)
   if {[file extension $file] == ".json"} {
     read_json $file
   } else {
     read_rtlil $file
-  }
-} else {
+  }  
+}
+
+proc read_design_sources {} {
   # We are reading Verilog sources
   source $::env(SCRIPTS_DIR)/synth_stdcells.tcl