1+ source $::env(SCRIPTS_DIR) /util.tcl
2+
13foreach libFile $::env(LIB_FILES) {
24 if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile ] == -1} {
35 read_liberty $libFile
46 }
57}
68
7- read_verilog results/asap7/mock-array_Element/base/6_final.v
8- read_verilog $::env(RESULTS_DIR) /6_final.v
9- read_verilog $::env(PLATFORM_DIR) /verilog/stdcell/empty.v
10-
11- link_design MockArray
9+ log_cmd read_verilog results/asap7/mock-array_Element/base/6_final.v
10+ log_cmd read_verilog $::env(RESULTS_DIR) /6_final.v
11+ log_cmd read_verilog $::env(PLATFORM_DIR) /verilog/stdcell/empty.v
12+ log_cmd link_design MockArray
1213
13- read_sdc $::env(RESULTS_DIR) /6_final.sdc
14- read_spef $::env(RESULTS_DIR) /6_final.spef
14+ log_cmd read_sdc $::env(RESULTS_DIR) /6_final.sdc
15+ log_cmd read_spef $::env(RESULTS_DIR) /6_final.spef
16+ puts " read_spef for ces_*_* macros"
1517for {set x 0} {$x < 8} {incr x} {
1618 for {set y 0} {$y < 8} {incr y} {
1719 read_spef -path ces_${x} _${y} results/asap7/mock-array_Element/base/6_final.spef
1820 }
1921}
2022
21- report_parasitic_annotation
22- report_power
23- read_vcd -scope TOP/MockArray $::env(RESULTS_DIR) /MockArrayTestbench.vcd
23+ log_cmd report_power
24+ log_cmd read_vcd -scope TOP/MockArray $::env(RESULTS_DIR) /MockArrayTestbench.vcd
2425
2526set ces {}
2627for {set x 0} {$x < 8} {incr x} {
@@ -29,5 +30,9 @@ for {set x 0} {$x < 8} {incr x} {
2930 }
3031}
3132
33+ puts {report_power -instances [get_cells $ces ]}
3234report_power -instances [get_cells $ces ]
33- report_power
35+ log_cmd report_power
36+
37+ log_cmd report_parasitic_annotation
38+ log_cmd report_activity_annotation -report_unannotated
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