make: moved nangate45 to python

$ DESIGN_NAME=gcd CORE_UTILIZATION=55 PLACE_DENSITY_LB_ADDON=0.20 PLATFORM=nangate45 PLATFORM_DIR=platforms/nangate45 scripts/flow.sh 2_1_floorplan floorplan
Running floorplan.tcl, stage 2_1_floorplan
[INFO ODB-0227] LEF file: platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias
[INFO ODB-0227] LEF file: platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef, created 135 library cells

==========================================================================
Floorplan check_setup
--------------------------------------------------------------------------
number instances in verilog is 503
[WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.140, 1.400).
[INFO IFP-0001] Added 24 rows of 180 site FreePDK45_38x28_10R_NP_162NW_34O.
repair_timing -verbose -setup_margin 0 -repair_tns 100
[WARNING RSZ-0021] no estimated parasitics. Using wire load models.
[INFO RSZ-0098] No setup violations found
[INFO RSZ-0033] No hold violations found.
Default units for flow
 time 1ns
 capacitance 1fF
 resistance 1kohm
 voltage 1v
 current 1mA
 power 1nW
 distance 1um
Report metrics stage 2, floorplan final...

==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 650 u^2 57% utilization.
Elapsed time: 0:00.40[h:]min:sec. CPU time: user 0.33 sys 0.09 (106%). Peak memory: 121724KB.

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/Makefile

@@ -201,6 +201,9 @@ $(foreach line,$(shell \
   YOSYS_EXE=$(YOSYS_EXE) \
   KLAYOUT_CMD=$(KLAYOUT_CMD) \
   SCRIPTS_DIR=$(SCRIPTS_DIR) \
+  ADDITIONAL_LIBS=$(ADDITIONAL_LIBS) \
+  ADDITIONAL_LIBS=$(ADDITIONAL_GDS) \
+  ADDITIONAL_LIBS=$(ADDITIONAL_LEFS) \
   $(SCRIPTS_DIR)/defaults.py make),$(eval export $(subst __SPACE__, ,$(line))))
 
 # Not normally adjusted by user

flow/platforms/nangate45/config.mk

@@ -1,4 +1,93 @@
-def get_defaults():
+import glob
+import os
+
+
+def get_defaults(variables):
+    gds_files = (
+        " ".join(
+            sorted(glob.glob(os.path.join(variables["PLATFORM_DIR"], "gds", "*.gds")))
+        )
+        + " "
+        + variables.get("ADDITIONAL_GDS", "")
+    ).strip()
     return {
         "PROCESS": "45",
+        # -----------------------------------------------------
+        # Tech/Libs
+        # -----------------------------------------------------
+        "TECH_LEF": f"{variables['PLATFORM_DIR']}/lef/NangateOpenCellLibrary.tech.lef",
+        "SC_LEF": f"{variables['PLATFORM_DIR']}/lef/NangateOpenCellLibrary.macro.mod.lef",
+        "LIB_FILES": f"{variables['PLATFORM_DIR']}/lib/NangateOpenCellLibrary_typical.lib {variables.get('ADDITIONAL_LIBS', '')}",
+        "GDS_FILES": gds_files,
+        # Don't use cells to ease congestion
+        # Specify at least one filler cell if none
+        "DONT_USE_CELLS": "TAPCELL_X1 FILLCELL_X1 AOI211_X1 OAI211_X1",
+        # Fill cells used in fill cell insertion
+        "FILL_CELLS": "FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8 FILLCELL_X16 FILLCELL_X32",
+        # -----------------------------------------------------
+        # Yosys
+        # -----------------------------------------------------
+        # Ungroup size for hierarchical synthesis
+        "SYNTH_MINIMUM_KEEP_SIZE": 10000,
+        # Set the TIEHI/TIELO cells
+        # These are used in yosys synthesis to avoid logical 1/0's in the netlist
+        "TIEHI_CELL_AND_PORT": "LOGIC1_X1 Z",
+        "TIELO_CELL_AND_PORT": "LOGIC0_X1 Z",
+        # Used in synthesis
+        "MIN_BUF_CELL_AND_PORTS": "BUF_X1 A Z",
+        # Yosys mapping files
+        "LATCH_MAP_FILE": f"{variables['PLATFORM_DIR']}/cells_latch.v",
+        "CLKGATE_MAP_FILE": f"{variables['PLATFORM_DIR']}/cells_clkgate.v",
+        "ADDER_MAP_FILE": f"{variables['PLATFORM_DIR']}/cells_adders.v",
+        "ABC_DRIVER_CELL": "BUF_X1",
+        # BUF_X1, pin (A) = 0.974659. Arbitrarily multiply by 4
+        "ABC_LOAD_IN_FF": 3.898,
+        # --------------------------------------------------------
+        # Floorplan
+        # --------------------------------------------------------
+        # Placement site for core cells
+        # This can be found in the technology lef
+        "PLACE_SITE": "FreePDK45_38x28_10R_NP_162NW_34O",
+        # IO Placer pin layers
+        "IO_PLACER_H": "metal5",
+        "IO_PLACER_V": "metal6",
+        # Define default PDN config
+        "PDN_TCL": f"{variables['PLATFORM_DIR']}/grid_strategy-M1-M4-M7.tcl",
+        # Endcap and Welltie cells
+        "TAPCELL_TCL": f"{variables['PLATFORM_DIR']}/tapcell.tcl",
+        "TAP_CELL_NAME": "TAPCELL_X1",
+        "MACRO_PLACE_HALO": "22.4 15.12",
+        # ---------------------------------------------------------
+        # Place
+        # ---------------------------------------------------------
+        "PLACE_DENSITY": 0.30,
+        # ---------------------------------------------------------
+        # Route
+        # ---------------------------------------------------------
+        # FastRoute options
+        "MIN_ROUTING_LAYER": "metal2",
+        "MAX_ROUTING_LAYER": "metal10",
+        # Define fastRoute tcl
+        "FASTROUTE_TCL": f"{variables['PLATFORM_DIR']}/fastroute.tcl",
+        # KLayout technology file
+        "KLAYOUT_TECH_FILE": f"{variables['PLATFORM_DIR']}/FreePDK45.lyt",
+        # KLayout DRC ruledeck
+        "KLAYOUT_DRC_FILE": f"{variables['PLATFORM_DIR']}/drc/FreePDK45.lydrc",
+        # KLayout LVS ruledeck
+        "KLAYOUT_LVS_FILE": f"{variables['PLATFORM_DIR']}/lvs/FreePDK45.lylvs",
+        # Allow empty GDS cell
+        "GDS_ALLOW_EMPTY": "fakeram.*",
+        "CDL_FILE": f"{variables['PLATFORM_DIR']}/cdl/NangateOpenCellLibrary.cdl",
+        # Template definition for power grid analysis
+        "TEMPLATE_PGA_CFG": f"{variables['PLATFORM_DIR']}/template_pga.cfg",
+        # OpenRCX extRules
+        "RCX_RULES": f"{variables['PLATFORM_DIR']}/rcx_patterns.rules",
+        # ---------------------------------------------------------
+        # IR Drop
+        # ---------------------------------------------------------
+        # IR drop estimation supply net name to be analyzed and supply voltage variable
+        # For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2"
+        "PWR_NETS_VOLTAGES": "VDD 1.1",
+        "GND_NETS_VOLTAGES": "VSS 0.0",
+        "IR_DROP_LAYER": "metal1",
     }

flow/platforms/nangate45/config.py

@@ -10,7 +10,7 @@
     sys.path.append(os.path.dirname(config_py))
     import config
 
-    platform_defaults = config.get_defaults()
+    platform_defaults = config.get_defaults(os.environ)
 else:
     platform_defaults = {}