Merge pull request #1345 from Pinata-Consulting/mock-alu

asap7/mock-alu: a mock ALU with registered inputs and outputs

Author: maliberty

flow/designs/asap7/mock-alu/README.md

@@ -0,0 +1,7 @@
+Mock ALU
+========
+
+A mock ALU that can be configured in different sizes to generate
+interesting test-cases.
+
+By default, the ALU is 64 bit wide.

flow/designs/asap7/mock-alu/autotuner.json

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+{
+    "_SDC_FILE_PATH": "constraints.sdc",
+    "_SDC_CLK_PERIOD": {
+        "type": "float",
+        "minmax": [
+            0.1,
+            0.4
+        ],
+        "step": 0
+    },
+    "CORE_UTILIZATION": {
+        "type": "int",
+        "minmax": [
+            5,
+            100
+        ],
+        "step": 1
+    },
+    "CORE_ASPECT_RATIO": {
+        "type": "float",
+        "minmax": [
+            0.5,
+            2.0
+        ],
+        "step": 0
+    },
+    "CORE_MARGIN": {
+        "type": "int",
+        "minmax": [
+            2,
+            2
+        ],
+        "step": 0
+    },
+    "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            5
+        ],
+        "step": 1
+    },
+    "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            5
+        ],
+        "step": 1
+    },
+    "_FR_LAYER_ADJUST": {
+        "type": "float",
+        "minmax": [
+            0.1,
+            0.7
+        ],
+        "step": 0
+    },
+    "PLACE_DENSITY_LB_ADDON": {
+        "type": "float",
+        "minmax": [
+            0.0,
+            0.99
+        ],
+        "step": 0
+    },
+    "_PINS_DISTANCE": {
+        "type": "int",
+        "minmax": [
+            1,
+            4
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_SIZE": {
+        "type": "int",
+        "minmax": [
+            10,
+            200
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_DIAMETER": {
+        "type": "int",
+        "minmax": [
+            20,
+            400
+        ],
+        "step": 1
+    },
+    "_FR_FILE_PATH": "",
+    "_FR_GR_OVERFLOW": {
+        "type": "int",
+        "minmax": [
+            1,
+            1
+        ],
+        "step": 0
+    }
+}

flow/designs/asap7/mock-alu/config.mk

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+include designs/asap7/mock-alu/defaults.mk
+
+export DESIGN_NAME            = MockAlu
+export DESIGN_NICKNAME        = mock-alu
+
+export VERILOG_FILES          = designs/src/mock-alu/*.v
+
+export SDC_FILE               = designs/asap7/mock-alu/constraints.sdc
+
+export PLATFORM               = asap7
+
+export PLACE_DENSITY          = 0.60
+export CORE_UTILIZATION       = 40
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+
+verilog:
+	export MOCK_ALU_WIDTH=$(word 1, $(MOCK_ALU_WIDTH)) ; \
+	./designs/asap7/mock-alu/verilog.sh

flow/designs/asap7/mock-alu/constraints.sdc

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+set clk_name clock
+set clk_port_name clock
+set clk_period 500
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period  $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/asap7/mock-alu/defaults.mk

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+export MOCK_ALU_WIDTH     ?= 64