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jeffng-orjeffng-or
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Added mempool_group SV in prep for SV enablement
removed references to GF12 memories, which were already commented out removed extra backslash removed metadata and rules files Signed-off-by: Jeff Ng <[email protected]>
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‎flow/designs/nangate45/mempool_group/config.mk‎

Lines changed: 61 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,23 +5,73 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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export TEMP_DESIGN_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)
8-
export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v
8+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_group.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/cf_math_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi_hier_interco.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_tile.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_mux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_remap.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_cc.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fall_through_register.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_xbar.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/address_scrambler.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_shim.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_axi_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_cut.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_intf.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/riscv_instr.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_prepend.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/rr_arb_tree.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fifo_v3.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/lzc.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_ipu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/isochronous_spill_register.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/onehot_to_bin.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/fifo_v2.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register_flushable.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter_flushable.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/latch_scm.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_lsu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch_addr_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_regfile_ff.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_shared_muldiv.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/find_first_one.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_onehot.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv
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export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/register_interface/include
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x32.lef \
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$(PLATFORM_DIR)/lef/fakeram45_64x64.lef \
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$(PLATFORM_DIR)/lef/fakeram45_128x32.lef \
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$(PLATFORM_DIR)/lef/fakeram45_128x256.lef
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$(PLATFORM_DIR)/lef/fakeram45_64x64.lef
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export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x32.lib \
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$(PLATFORM_DIR)/lib/fakeram45_128x32.lib \
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$(PLATFORM_DIR)/lib/fakeram45_64x64.lib \
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$(PLATFORM_DIR)/lib/fakeram45_128x256.lib
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$(PLATFORM_DIR)/lib/fakeram45_64x64.lib
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22-
export DIE_AREA = 0 0 4400 4400
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export CORE_AREA = 10 12 4390 4390
72+
export DIE_AREA = 0 0 1100 1100
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export CORE_AREA = 10 12 1090 1090
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25-
export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-1000 -exclude bottom:3400-4400
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export MACRO_PLACE_HALO = 10 10
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export MACRO_PLACE_HALO = 10 10
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export SYNTH_USE_SLANG = 1

‎flow/designs/nangate45/mempool_group/mempool_group.sdc‎

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set sdc_version 2.0
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set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
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set clock_cycle 3
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set uncertainty [expr $clock_cycle*0.02]
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set io_delay 0
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set maxFanout 16
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set maxTransition [expr $clock_cycle*0.01]
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set pre_cts_clock_latency_estimate 0.070
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set clock_port_mempool_tile clk_i
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create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
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set_clock_uncertainty $uncertainty [all_clocks]
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set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
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set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
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set_max_transition $maxTransition -clock_path [get_clocks clk_i]
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set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
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#set_propagated_clock [get_clocks clk_i]
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# Create virtual clock.
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create_clock -name "vclk_i" -period $clock_cycle
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set_clock_uncertainty $uncertainty [get_clocks vclk_i]
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set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
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set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
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set_case_analysis 0 [get_ports scan_enable_i]
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set_max_fanout $maxFanout [current_design]
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# False path some of the quasi-static signals.
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#set_false_path -from tile_id_i
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# TCDM Master
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set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}]
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set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}]
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# TCDM Slave
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#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}]
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set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}]
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# Refill port
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#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}]
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#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}]
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# Reset
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set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
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# Critical range
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# Depending on the synthesis tool used, this can be helpful.
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#set_critical_range 0.100 [current_design]

‎flow/designs/src/mempool_group/README.md‎

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1+
Extracted from https://github.com/TILOS-AI-Institute/MacroPlacement

‎flow/designs/src/mempool_group/rtl/address_scrambler.sv‎

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Original file line numberDiff line numberDiff line change
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// Copyright 2021 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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// Description: Scrambles the address in such a way, that part of the memory is accessed
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// sequentially and part is interleaved.
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// Current constraints:
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// Author: Samuel Riedel <[email protected]>
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module address_scrambler #(
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parameter int unsigned AddrWidth = 32,
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parameter int unsigned ByteOffset = 2,
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parameter int unsigned NumTiles = 2,
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parameter int unsigned NumBanksPerTile = 2,
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parameter bit Bypass = 0,
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parameter int unsigned SeqMemSizePerTile = 4*1024
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) (
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input logic [AddrWidth-1:0] address_i,
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output logic [AddrWidth-1:0] address_o
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);
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localparam int unsigned BankOffsetBits = $clog2(NumBanksPerTile);
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localparam int unsigned TileIdBits = $clog2(NumTiles);
24+
localparam int unsigned SeqPerTileBits = $clog2(SeqMemSizePerTile);
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localparam int unsigned SeqTotalBits = SeqPerTileBits+TileIdBits;
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localparam int unsigned ConstantBitsLSB = ByteOffset + BankOffsetBits;
27+
localparam int unsigned ScrambleBits = SeqPerTileBits-ConstantBitsLSB;
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if (Bypass || NumTiles < 2) begin
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assign address_o = address_i;
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end else begin
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logic [ScrambleBits-1:0] scramble; // Address bits that have to be shuffled around
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logic [TileIdBits-1:0] tile_id; // Which tile does this address region belong to
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// Leave this part of the address unchanged
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// The LSBs that correspond to the offset inside a tile. These are the byte offset (bank width)
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// and the Bank offset (Number of Banks in tile)
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assign address_o[ConstantBitsLSB-1:0] = address_i[ConstantBitsLSB-1:0];
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// The MSBs that are outside of the sequential memory size. Currently the sequential memory size
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// always starts at 0. These are all the MSBs up to SeqMemSizePerTile*NumTiles
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assign address_o[AddrWidth-1:SeqTotalBits] = address_i[AddrWidth-1:SeqTotalBits];
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// Scramble the middle part
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// Bits that would have gone to different tiles but now go to increasing lines in the same tile
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assign scramble = address_i[SeqPerTileBits-1:ConstantBitsLSB]; // Bits that would
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// Bits that would have gone to increasing lines in the same tile but now go to different tiles
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assign tile_id = address_i[SeqTotalBits-1:SeqPerTileBits];
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always_comb begin
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// Default: Unscrambled
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address_o[SeqTotalBits-1:ConstantBitsLSB] = {tile_id, scramble};
52+
// If not in bypass mode and address is in sequential region and more than one tile
53+
if (address_i < (NumTiles * SeqMemSizePerTile)) begin
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address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id};
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end
56+
end
57+
end
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// Check for unsupported configurations
60+
if (NumBanksPerTile < 2)
61+
$fatal(1, "NumBanksPerTile must be greater than 2. The special case '1' is currently not supported!");
62+
if (SeqMemSizePerTile % (2**ByteOffset*NumBanksPerTile) != 0)
63+
$fatal(1, "SeqMemSizePerTile must be a multiple of BankWidth*NumBanksPerTile!");
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endmodule : address_scrambler

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