99 "cts__clock__skew__setup" : 0.6099 ,
1010 "cts__clock__skew__setup__post_repair" : 0.6156 ,
1111 "cts__clock__skew__setup__pre_repair" : 0.6156 ,
12- "cts__design__instance__area" : 1535446.625 ,
12+ "cts__design__instance__area" : 1557498.75 ,
1313 "cts__design__instance__area__macros" : 561467.5 ,
1414 "cts__design__instance__area__macros__post_repair" : 561467.5 ,
1515 "cts__design__instance__area__macros__pre_repair" : 561467.5 ,
1616 "cts__design__instance__area__post_repair" : 1515398.375 ,
1717 "cts__design__instance__area__pre_repair" : 1515365.75 ,
18- "cts__design__instance__area__stdcell" : 973979.0625 ,
18+ "cts__design__instance__area__stdcell" : 996031.1875 ,
1919 "cts__design__instance__area__stdcell__post_repair" : 953930.875 ,
2020 "cts__design__instance__area__stdcell__pre_repair" : 953898.25 ,
21- "cts__design__instance__count" : 128113 ,
22- "cts__design__instance__count__hold_buffer" : 2893 .0 ,
21+ "cts__design__instance__count" : 131356 ,
22+ "cts__design__instance__count__hold_buffer" : 6136 .0 ,
2323 "cts__design__instance__count__macros" : 24 ,
2424 "cts__design__instance__count__macros__post_repair" : 24 ,
2525 "cts__design__instance__count__macros__pre_repair" : 24 ,
2626 "cts__design__instance__count__post_repair" : 125180 ,
2727 "cts__design__instance__count__pre_repair" : 125178 ,
2828 "cts__design__instance__count__setup_buffer" : 40.0 ,
29- "cts__design__instance__count__stdcell" : 128089 ,
29+ "cts__design__instance__count__stdcell" : 131332 ,
3030 "cts__design__instance__count__stdcell__post_repair" : 125156 ,
3131 "cts__design__instance__count__stdcell__pre_repair" : 125154 ,
32- "cts__design__instance__displacement__max" : 49.214 ,
33- "cts__design__instance__displacement__mean" : 0.2985 ,
34- "cts__design__instance__displacement__total" : 38251.938 ,
35- "cts__design__instance__utilization" : 0.3562 ,
32+ "cts__design__instance__displacement__max" : 115.2 ,
33+ "cts__design__instance__displacement__mean" : 1.0085 ,
34+ "cts__design__instance__displacement__total" : 132500.6375 ,
35+ "cts__design__instance__utilization" : 0.3613 ,
3636 "cts__design__instance__utilization__post_repair" : 0.3515 ,
3737 "cts__design__instance__utilization__pre_repair" : 0.3515 ,
38- "cts__design__instance__utilization__stdcell" : 0.2597 ,
38+ "cts__design__instance__utilization__stdcell" : 0.2656 ,
3939 "cts__design__instance__utilization__stdcell__post_repair" : 0.2544 ,
4040 "cts__design__instance__utilization__stdcell__pre_repair" : 0.2544 ,
4141 "cts__design__io" : 1198 ,
4242 "cts__design__io__post_repair" : 1198 ,
4343 "cts__design__io__pre_repair" : 1198 ,
4444 "cts__design__violations" : 0 ,
45- "cts__power__internal__total" : 0.0758 ,
46- "cts__power__internal__total__post_repair" : 0.0753 ,
47- "cts__power__internal__total__pre_repair" : 0.0753 ,
45+ "cts__power__internal__total" : 0.076 ,
46+ "cts__power__internal__total__post_repair" : 0.0748 ,
47+ "cts__power__internal__total__pre_repair" : 0.0748 ,
4848 "cts__power__leakage__total" : 0.0007 ,
4949 "cts__power__leakage__total__post_repair" : 0.0007 ,
5050 "cts__power__leakage__total__pre_repair" : 0.0007 ,
51- "cts__power__switching__total" : 0.0627 ,
52- "cts__power__switching__total__post_repair" : 0.0623 ,
53- "cts__power__switching__total__pre_repair" : 0.0622 ,
54- "cts__power__total" : 0.1392 ,
55- "cts__power__total__post_repair" : 0.1382 ,
56- "cts__power__total__pre_repair" : 0.1381 ,
57- "cts__route__wirelength__estimated" : 6616521.8145 ,
51+ "cts__power__switching__total" : 0.0619 ,
52+ "cts__power__switching__total__post_repair" : 0.0613 ,
53+ "cts__power__switching__total__pre_repair" : 0.0613 ,
54+ "cts__power__total" : 0.1386 ,
55+ "cts__power__total__post_repair" : 0.1369 ,
56+ "cts__power__total__pre_repair" : 0.1368 ,
57+ "cts__route__wirelength__estimated" : 6700129.3965 ,
5858 "cts__timing__drv__hold_violation_count" : 0 ,
5959 "cts__timing__drv__hold_violation_count__post_repair" : 1 ,
6060 "cts__timing__drv__hold_violation_count__pre_repair" : 1 ,
7979 "cts__timing__drv__setup_violation_count" : 1 ,
8080 "cts__timing__drv__setup_violation_count__post_repair" : 1 ,
8181 "cts__timing__drv__setup_violation_count__pre_repair" : 1 ,
82- "cts__timing__setup__tns" : -955.72 ,
82+ "cts__timing__setup__tns" : -2278.8601 ,
8383 "cts__timing__setup__tns__post_repair" : -1683.5 ,
8484 "cts__timing__setup__tns__pre_repair" : -1843.02 ,
8585 "cts__timing__setup__ws" : -1.63 ,
8686 "cts__timing__setup__ws__post_repair" : -2.49 ,
8787 "cts__timing__setup__ws__pre_repair" : -2.76 ,
88- "detailedplace__cpu__total" : 90.18 ,
88+ "detailedplace__cpu__total" : 116.69 ,
8989 "detailedplace__design__instance__area" : 1508084.125 ,
9090 "detailedplace__design__instance__area__macros" : 561467.5 ,
9191 "detailedplace__design__instance__area__stdcell" : 946616.625 ,
9999 "detailedplace__design__instance__utilization__stdcell" : 0.2525 ,
100100 "detailedplace__design__io" : 1198 ,
101101 "detailedplace__design__violations" : 0 ,
102- "detailedplace__mem__peak" : 1283332 .0 ,
103- "detailedplace__power__internal__total" : 0.0721 ,
102+ "detailedplace__mem__peak" : 1326492 .0 ,
103+ "detailedplace__power__internal__total" : 0.0716 ,
104104 "detailedplace__power__leakage__total" : 0.0007 ,
105- "detailedplace__power__switching__total" : 0.0442 ,
106- "detailedplace__power__total" : 0.117 ,
105+ "detailedplace__power__switching__total" : 0.0433 ,
106+ "detailedplace__power__total" : 0.1156 ,
107107 "detailedplace__route__wirelength__estimated" : 6542794.607 ,
108- "detailedplace__runtime__total" : " 1:31.54 " ,
108+ "detailedplace__runtime__total" : " 2:06.15 " ,
109109 "detailedplace__timing__drv__hold_violation_count" : 1 ,
110110 "detailedplace__timing__drv__max_cap" : 1 ,
111111 "detailedplace__timing__drv__max_cap_limit" : -0.0015 ,
117117 "detailedplace__timing__setup__tns" : -3420.3201 ,
118118 "detailedplace__timing__setup__ws" : -2.4 ,
119119 "detailedroute__route__drc_errors" : 0 ,
120- "detailedroute__route__drc_errors__iter:1" : 52305 ,
121- "detailedroute__route__drc_errors__iter:2" : 9828 ,
122- "detailedroute__route__drc_errors__iter:3" : 7629 ,
123- "detailedroute__route__drc_errors__iter:4" : 51 ,
124- "detailedroute__route__drc_errors__iter:5" : 12 ,
125- "detailedroute__route__drc_errors__iter:6" : 0 ,
126- "detailedroute__route__net" : 111063 ,
120+ "detailedroute__route__drc_errors__iter:1" : 53050 ,
121+ "detailedroute__route__drc_errors__iter:2" : 9898 ,
122+ "detailedroute__route__drc_errors__iter:3" : 7798 ,
123+ "detailedroute__route__drc_errors__iter:4" : 61 ,
124+ "detailedroute__route__drc_errors__iter:5" : 17 ,
125+ "detailedroute__route__drc_errors__iter:6" : 8 ,
126+ "detailedroute__route__drc_errors__iter:7" : 2 ,
127+ "detailedroute__route__drc_errors__iter:8" : 1 ,
128+ "detailedroute__route__drc_errors__iter:9" : 0 ,
129+ "detailedroute__route__net" : 114306 ,
127130 "detailedroute__route__net__special" : 2 ,
128- "detailedroute__route__vias" : 860953 ,
131+ "detailedroute__route__vias" : 878199 ,
129132 "detailedroute__route__vias__multicut" : 0 ,
130- "detailedroute__route__vias__singlecut" : 860953 ,
131- "detailedroute__route__wirelength" : 7764846 ,
132- "detailedroute__route__wirelength__iter:1" : 7791136 ,
133- "detailedroute__route__wirelength__iter:2" : 7771318 ,
134- "detailedroute__route__wirelength__iter:3" : 7764933 ,
135- "detailedroute__route__wirelength__iter:4" : 7764860 ,
136- "detailedroute__route__wirelength__iter:5" : 7764852 ,
137- "detailedroute__route__wirelength__iter:6" : 7764846 ,
138- "finish__clock__skew__hold" : -0.4451 ,
139- "finish__clock__skew__setup" : -0.4451 ,
140- "finish__cpu__total" : 178.62 ,
141- "finish__design__instance__area" : 1535446.625 ,
133+ "detailedroute__route__vias__singlecut" : 878199 ,
134+ "detailedroute__route__wirelength" : 7850289 ,
135+ "detailedroute__route__wirelength__iter:1" : 7876669 ,
136+ "detailedroute__route__wirelength__iter:2" : 7856816 ,
137+ "detailedroute__route__wirelength__iter:3" : 7850409 ,
138+ "detailedroute__route__wirelength__iter:4" : 7850303 ,
139+ "detailedroute__route__wirelength__iter:5" : 7850297 ,
140+ "detailedroute__route__wirelength__iter:6" : 7850293 ,
141+ "detailedroute__route__wirelength__iter:7" : 7850288 ,
142+ "detailedroute__route__wirelength__iter:8" : 7850290 ,
143+ "detailedroute__route__wirelength__iter:9" : 7850289 ,
144+ "finish__clock__skew__hold" : -0.4423 ,
145+ "finish__clock__skew__setup" : -0.4423 ,
146+ "finish__cpu__total" : 177.59 ,
147+ "finish__design__instance__area" : 1557498.75 ,
142148 "finish__design__instance__area__macros" : 561467.5 ,
143- "finish__design__instance__area__stdcell" : 973979.0625 ,
144- "finish__design__instance__count" : 128113 ,
149+ "finish__design__instance__area__stdcell" : 996031.1875 ,
150+ "finish__design__instance__count" : 131356 ,
145151 "finish__design__instance__count__macros" : 24 ,
146- "finish__design__instance__count__stdcell" : 128089 ,
147- "finish__design__instance__utilization" : 0.3562 ,
148- "finish__design__instance__utilization__stdcell" : 0.2597 ,
152+ "finish__design__instance__count__stdcell" : 131332 ,
153+ "finish__design__instance__utilization" : 0.3613 ,
154+ "finish__design__instance__utilization__stdcell" : 0.2656 ,
149155 "finish__design__io" : 1198 ,
150- "finish__mem__peak" : 2949932 .0 ,
151- "finish__power__internal__total" : 0.0763 ,
156+ "finish__mem__peak" : 3039764 .0 ,
157+ "finish__power__internal__total" : 0.0766 ,
152158 "finish__power__leakage__total" : 0.0007 ,
153- "finish__power__switching__total" : 0.0462 ,
159+ "finish__power__switching__total" : 0.0457 ,
154160 "finish__power__total" : 0.1231 ,
155- "finish__runtime__total" : " 3:02.13 " ,
161+ "finish__runtime__total" : " 3:01.19 " ,
156162 "finish__timing__drv__hold_violation_count" : 1.0 ,
157163 "finish__timing__drv__max_cap" : 0 ,
158- "finish__timing__drv__max_cap_limit" : 0.2357 ,
164+ "finish__timing__drv__max_cap_limit" : 0.2378 ,
159165 "finish__timing__drv__max_fanout" : 0 ,
160166 "finish__timing__drv__max_fanout_limit" : 1.0000000150474662e+30 ,
161167 "finish__timing__drv__max_slew" : 0 ,
162- "finish__timing__drv__max_slew_limit" : 0.373 ,
168+ "finish__timing__drv__max_slew_limit" : 0.3766 ,
163169 "finish__timing__drv__setup_violation_count" : 1.0 ,
164- "finish__timing__setup__tns" : -64.31 ,
165- "finish__timing__setup__ws" : -0.41 ,
166- "finish__timing__wns_percent_delay" : -4.559625 ,
167- "floorplan__cpu__total" : 20.59 ,
170+ "finish__timing__setup__tns" : -1118.1 ,
171+ "finish__timing__setup__ws" : -1.52 ,
172+ "finish__timing__wns_percent_delay" : -16.092136 ,
173+ "floorplan__cpu__total" : 20.2 ,
168174 "floorplan__design__instance__area" : 1237809.625 ,
169175 "floorplan__design__instance__area__macros" : 561467.5 ,
170176 "floorplan__design__instance__area__stdcell" : 676342.0625 ,
174180 "floorplan__design__instance__utilization" : 0.2871 ,
175181 "floorplan__design__instance__utilization__stdcell" : 0.1804 ,
176182 "floorplan__design__io" : 1198 ,
177- "floorplan__mem__peak" : 712608 .0 ,
178- "floorplan__power__internal__total" : 0.0718 ,
183+ "floorplan__mem__peak" : 753428 .0 ,
184+ "floorplan__power__internal__total" : 0.0711 ,
179185 "floorplan__power__leakage__total" : 0.0005 ,
180- "floorplan__power__switching__total" : 0.0115 ,
181- "floorplan__power__total" : 0.0838 ,
182- "floorplan__runtime__total" : " 0:21.18 " ,
186+ "floorplan__power__switching__total" : 0.0112 ,
187+ "floorplan__power__total" : 0.0828 ,
188+ "floorplan__runtime__total" : " 0:29.22 " ,
183189 "floorplan__timing__setup__tns" : -177517.875 ,
184190 "floorplan__timing__setup__ws" : -26.3 ,
185191 "globalplace__design__instance__area" : 1256258.875 ,
191197 "globalplace__design__instance__utilization" : 0.2914 ,
192198 "globalplace__design__instance__utilization__stdcell" : 0.1853 ,
193199 "globalplace__design__io" : 1198 ,
194- "globalplace__power__internal__total" : 0.0918 ,
200+ "globalplace__power__internal__total" : 0.091 ,
195201 "globalplace__power__leakage__total" : 0.0005 ,
196- "globalplace__power__switching__total" : 0.0377 ,
197- "globalplace__power__total" : 0.1299 ,
202+ "globalplace__power__switching__total" : 0.0368 ,
203+ "globalplace__power__total" : 0.1283 ,
198204 "globalplace__timing__setup__tns" : -1041706.0 ,
199205 "globalplace__timing__setup__ws" : -168.27 ,
200- "globalroute__clock__skew__hold" : 0.6043 ,
201- "globalroute__clock__skew__setup" : 0.6043 ,
202- "globalroute__design__instance__area" : 1535446.625 ,
206+ "globalroute__clock__skew__hold" : 0.6171 ,
207+ "globalroute__clock__skew__setup" : 0.6171 ,
208+ "globalroute__design__instance__area" : 1557498.75 ,
203209 "globalroute__design__instance__area__macros" : 561467.5 ,
204- "globalroute__design__instance__area__stdcell" : 973979.0625 ,
205- "globalroute__design__instance__count" : 128113 ,
210+ "globalroute__design__instance__area__stdcell" : 996031.1875 ,
211+ "globalroute__design__instance__count" : 131356 ,
206212 "globalroute__design__instance__count__macros" : 24 ,
207- "globalroute__design__instance__count__stdcell" : 128089 ,
208- "globalroute__design__instance__utilization" : 0.3562 ,
209- "globalroute__design__instance__utilization__stdcell" : 0.2597 ,
213+ "globalroute__design__instance__count__stdcell" : 131332 ,
214+ "globalroute__design__instance__utilization" : 0.3613 ,
215+ "globalroute__design__instance__utilization__stdcell" : 0.2656 ,
210216 "globalroute__design__io" : 1198 ,
211- "globalroute__power__internal__total" : 0.0761 ,
217+ "globalroute__power__internal__total" : 0.0765 ,
212218 "globalroute__power__leakage__total" : 0.0007 ,
213- "globalroute__power__switching__total" : 0.0655 ,
214- "globalroute__power__total" : 0.1423 ,
215- "globalroute__timing__clock__slack" : -1.762 ,
216- "globalroute__timing__drv__hold_violation_count" : 1 ,
219+ "globalroute__power__switching__total" : 0.0649 ,
220+ "globalroute__power__total" : 0.1421 ,
221+ "globalroute__timing__clock__slack" : -1.902 ,
222+ "globalroute__timing__drv__hold_violation_count" : 0 ,
217223 "globalroute__timing__drv__max_cap" : 2 ,
218224 "globalroute__timing__drv__max_cap_limit" : -0.0153 ,
219225 "globalroute__timing__drv__max_fanout" : 0 ,
220226 "globalroute__timing__drv__max_fanout_limit" : 1.0000000150474662e+30 ,
221227 "globalroute__timing__drv__max_slew" : 0 ,
222- "globalroute__timing__drv__max_slew_limit" : 0.0064 ,
228+ "globalroute__timing__drv__max_slew_limit" : 0.0063 ,
223229 "globalroute__timing__drv__setup_violation_count" : 1 ,
224- "globalroute__timing__setup__tns" : -1124.73 ,
225- "globalroute__timing__setup__ws" : -1.76 ,
226- "placeopt__cpu__total" : 104.23 ,
230+ "globalroute__timing__setup__tns" : -3103.8301 ,
231+ "globalroute__timing__setup__ws" : -1.9 ,
232+ "placeopt__cpu__total" : 108.49 ,
227233 "placeopt__design__instance__area" : 1508084.125 ,
228234 "placeopt__design__instance__area__macros" : 561467.5 ,
229235 "placeopt__design__instance__area__macros__pre_opt" : 561467.5 ,
242248 "placeopt__design__instance__utilization__stdcell__pre_opt" : 0.1853 ,
243249 "placeopt__design__io" : 1198 ,
244250 "placeopt__design__io__pre_opt" : 1198 ,
245- "placeopt__mem__peak" : 1075536 .0 ,
246- "placeopt__power__internal__total" : 0.0713 ,
247- "placeopt__power__internal__total__pre_opt" : 0.0918 ,
251+ "placeopt__mem__peak" : 1117344 .0 ,
252+ "placeopt__power__internal__total" : 0.0709 ,
253+ "placeopt__power__internal__total__pre_opt" : 0.091 ,
248254 "placeopt__power__leakage__total" : 0.0007 ,
249255 "placeopt__power__leakage__total__pre_opt" : 0.0005 ,
250- "placeopt__power__switching__total" : 0.0413 ,
251- "placeopt__power__switching__total__pre_opt" : 0.0377 ,
252- "placeopt__power__total" : 0.1133 ,
253- "placeopt__power__total__pre_opt" : 0.1299 ,
254- "placeopt__runtime__total" : " 1:45.44 " ,
256+ "placeopt__power__switching__total" : 0.0404 ,
257+ "placeopt__power__switching__total__pre_opt" : 0.0368 ,
258+ "placeopt__power__total" : 0.112 ,
259+ "placeopt__power__total__pre_opt" : 0.1283 ,
260+ "placeopt__runtime__total" : " 1:50.51 " ,
255261 "placeopt__timing__drv__hold_violation_count" : 1 ,
256262 "placeopt__timing__drv__max_cap" : 0 ,
257263 "placeopt__timing__drv__max_cap_limit" : 0.0018 ,
265271 "placeopt__timing__setup__ws" : -2.39 ,
266272 "placeopt__timing__setup__ws__pre_opt" : -168.27 ,
267273 "run__flow__design" : " bp" ,
268- "run__flow__generate_date" : " 2022-11-29 18 :27" ,
274+ "run__flow__generate_date" : " 2022-12-01 05 :27" ,
269275 "run__flow__metrics_version" : " Metrics_2.1.2" ,
270- "run__flow__openroad_commit" : " N/A" ,
271- "run__flow__openroad_version" : " v2.0-5851-g0769b42c9" ,
272276 "run__flow__platform" : " tsmc65lp" ,
273277 "run__flow__platform__capacitance_units" : " 1pF" ,
274278 "run__flow__platform__current_units" : " 1mA" ,
278282 "run__flow__platform__time_units" : " 1ns" ,
279283 "run__flow__platform__voltage_units" : " 1v" ,
280284 "run__flow__platform_commit" : " b25f2daf0825d34d8053a13141d30ac3424479e7" ,
281- "run__flow__scripts_commit" : " b939a9ed56b22fdbc33c988aa5644cfe48b5c4cb" ,
282- "run__flow__uuid" : " 5e70da41-6f57-4756-a28e-cd2690048082" ,
285+ "run__flow__uuid" : " 3701d4c4-8bf6-40cd-ade1-0cf12137c659" ,
283286 "run__flow__variant" : " base" ,
284- "synth__cpu__total" : 1040.31 ,
287+ "synth__cpu__total" : 1172.45 ,
285288 "synth__design__instance__area__stdcell" : 1274602.571001 ,
286289 "synth__design__instance__count__stdcell" : 109342.0 ,
287- "synth__mem__peak" : 11223480 .0 ,
288- "synth__runtime__total" : " 17:43.93 " ,
289- "total_time" : " 0:24:24.220000 "
290+ "synth__mem__peak" : 11280664 .0 ,
291+ "synth__runtime__total" : " 27:24.65 " ,
292+ "total_time" : " 0:34:51.720000 "
290293}
0 commit comments