Asap7 Platform With Fakeram Memory Model (#1110)

* Add - fakeram configurations for Megaboom design
        - both .lib and .lef
* Add README.md

Author: louiic

flow/platforms/asap7/README.md

@@ -0,0 +1,25 @@
+# Summary
+
+Version 1.7
+
+This package contain minimal file set require for designs, packaged under OpenROAD.
+This package also contain memory macro created from FakeRam2.0. The purpose of the
+memory macros is to complete OpenROAD design flow.
+
+FakeRam2.0 https://github.com/maliberty/FakeRAM2.0.git
+
+# Content
+
+The package contain
+
+	* lib     - timing libraries for both standard cells and memory macros
+	* lef     - LEF file format for physical design implementation for both
+                    stardard cells and memory macros
+	* verilog - verilog model for memory macros
+	* gds     - GDS for standard cells
+
+Along with data files, the package contain 
+
+	* PDN configuration for OpenROAD PG implementation
+	* tapcell.tcl - script for OpenROAD tap cell insertion
+	* KLayout technology files

flow/platforms/asap7/config.mk

@@ -234,13 +234,15 @@ ifeq ($(CORNER),)
    $(info Default PVT selection: $(CORNER))
    export LIB_FILES             += $($(CORNER)_LIB_FILES)
    export LIB_DIRS              += $($(CORNER)_LIB_DIRS)
+   export DB_FILES              += $(realpath $($(CORNER)_DB_FILES))
    export TEMPERATURE            = $($(CORNER)_TEMPERATURE)
    export VOLTAGE                = $($(CORNER)_VOLTAGE)
    export DONT_USE_SC_LIB        = $(OBJECTS_DIR)/lib/merged.lib
 else
    $(info User PVT selection: $(CORNER))
    export LIB_FILES             += $($(CORNER)_LIB_FILES)
    export LIB_DIRS              += $($(CORNER)_LIB_DIRS)
+   export DB_FILES              += $(realpath $($(CORNER)_DB_FILES))
    export TEMPERATURE            = $($(CORNER)_TEMPERATURE)
    export VOLTAGE                = $($(CORNER)_VOLTAGE)
    export DONT_USE_SC_LIB        = $(OBJECTS_DIR)/lib/merged.lib