Merge pull request #3364 from The-OpenROAD-Project-staging/tighten-rapidus-clk-period

updated clock periods for rapidus2hp designs to get negative slack

Author: maliberty

flow/designs/rapidus2hp/ethmac/constraint.sdc

@@ -22,7 +22,7 @@ set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
 
 set rx_clk_name mrx_clk_pad_i
 set rx_clk_port [get_ports $rx_clk_name]
-set rx_clk_period 300
+set rx_clk_period 200
 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
 set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
   $rx_clk_port]

flow/designs/rapidus2hp/gcd/constraint.sdc

@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name core_clock
 set clk_port_name clk
-set clk_period 185
+set clk_period 150
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]