updated asap7 cva6 memory sizes to remove tied off connections

updated metrics

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

flow/designs/asap7/cva6/config.mk

@@ -65,17 +65,26 @@ export VERILOG_FILES          = $(sort $(wildcard $(SRC_HOME)/common/local/util/
 	$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
 	$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
 	$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
-	$(PLATFORM_DIR)/verilog/fakeram7_256x256.sv
+	$(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_64x25.sv
 
 export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include
 
 export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
 
-export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x256.lef
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \
+			 $(PLATFORM_DIR)/lef/fakeram7_128x64.lef \
+			 $(PLATFORM_DIR)/lef/fakeram7_64x28.lef \
+			 $(PLATFORM_DIR)/lef/fakeram7_64x25.lef
 
-export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib
+export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \
+			 $(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \
+			 $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \
+			 $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib
 
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 

flow/designs/asap7/cva6/rules-base.json

@@ -1,38 +1,38 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 40631.65,
+        "value": 19930.01,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 45043,
+        "value": 23688,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 163049,
+        "value": 152015,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 14178,
+        "value": 13219,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 14178,
+        "value": 13219,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1884562,
+        "value": 1332082,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -216.36,
+        "value": -147.23,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 45315,
+        "value": 23925,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 7089,
+        "value": 6609,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 101,
+        "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -20.3,
+        "value": -16.08,
         "compare": ">="
     }
 }

flow/designs/src/cva6/README.md

@@ -1 +1,3 @@
 Extracted from https://github.com/openhwgroup/cva6
+
+Based on commit 3a389af with some changes for the RAMs

flow/designs/src/cva6/common/local/util/sram_cache.sv

@@ -52,7 +52,7 @@ module sram_cache #(
         rdata_o    = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH];
         ruser_o    = rdata_user[USER_WIDTH-1:0];
       end
-       fakeram7_256x256 i_tc_sram_wrapper(
+       fakeram7_64x256 i_tc_sram_wrapper(
         .clk    ( clk_i                     ),
         .ce_in    ( req_i                     ),
         .we_in     ( we_i                      ),
@@ -91,7 +91,7 @@ module sram_cache #(
         rdata_o    = rdata_user;
         ruser_o    = '0;
       end
-       fakeram7_256x256 i_tc_sram_wrapper(
+       fakeram7_64x25 i_tc_sram_wrapper(
         .clk    ( clk_i                     ),
         .ce_in    ( req_i                     ),
         .we_in     ( we_i                      ),

flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv

@@ -39,7 +39,7 @@ module hpdcache_sram
     output logic [DATA_SIZE-1:0]  rdata
 );
 
-    fakeram7_256x256 ram_i (
+    fakeram7_64x28 ram_i (
         .clk(clk),
         .ce_in(cs),
         .we_in(we),

flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv

@@ -39,7 +39,7 @@ module hpdcache_sram_wbyteenable
     input  logic [DATA_SIZE/8-1:0] wbyteenable,
     output logic [DATA_SIZE-1:0]   rdata
 );
-   fakeram7_256x256 ram_i (
+   fakeram7_128x64 ram_i (
         .clk (clk),
         .ce_in(cs),
         .we_in(we),