added some pin constraints to hercules_is_int

rebased to ff7980a
tcl formatting

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

docs/user/FlowVariables.md

@@ -347,6 +347,7 @@ configuration file.
 - [SKIP_REPAIR_TIE_FANOUT](#SKIP_REPAIR_TIE_FANOUT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SKIP_VT_SWAP](#SKIP_VT_SWAP)
+- [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND)
 - [TAPCELL_TCL](#TAPCELL_TCL)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)

flow/designs/rapidus2hp/hercules_is_int/config.mk

@@ -36,11 +36,11 @@ export CORE_MARGIN            = 1
 export PLACE_DENSITY          = 0.58
 
 export PLACE_PINS_ARGS = -min_distance_in_tracks -min_distance 1
-export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 0
-export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 0
 # temporarily skip over DPO to bypass one-site gap issues
 export ENABLE_DPO = 0
 
+export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/place_pins.tcl
+
 # Selectively keep module hierarchies to match baseline data
 # ifeq ($(SYNTH_HDL_FRONTEND), verific)
 #   export SYNTH_KEEP_MODULES = \hercules_is_grbt \