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mock-array: pipeline lsb does max four CEs before registering
Signed-off-by: Øyvind Harboe <[email protected]>
1 parent f603ae9 commit ce4e2cd

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2 files changed

+19
-3
lines changed

2 files changed

+19
-3
lines changed

flow/designs/src/mock-array/Element.v

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,15 @@ module Element(
2828
reg [63:0] REG_1;
2929
reg [63:0] REG_2;
3030
reg [63:0] REG_3;
31+
reg REG_4;
3132
assign io_outs_down = REG_3;
3233
assign io_outs_right = REG_2;
3334
assign io_outs_up = REG_1;
3435
assign io_outs_left = REG;
3536
assign io_lsbOuts_0 = io_lsbIns_1;
3637
assign io_lsbOuts_1 = io_lsbIns_2;
3738
assign io_lsbOuts_2 = io_lsbIns_3;
38-
assign io_lsbOuts_3 = io_lsbIns_4;
39+
assign io_lsbOuts_3 = REG_4;
3940
assign io_lsbOuts_4 = io_lsbIns_5;
4041
assign io_lsbOuts_5 = io_lsbIns_6;
4142
assign io_lsbOuts_6 = io_lsbIns_7;
@@ -45,5 +46,6 @@ module Element(
4546
REG_1 <= io_ins_right;
4647
REG_2 <= io_ins_up;
4748
REG_3 <= io_ins_left;
49+
REG_4 <= io_lsbIns_4;
4850
end
4951
endmodule

flow/designs/src/mock-array/src/test/scala/MockArray.scala

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,22 @@ class MockArray(width: Int, height: Int, singleElementWidth: Int)
7070
case (a, b) => a := b
7171
}
7272

73-
// Combinational logic
74-
io.lsbOuts := io.lsbIns.drop(1) ++ Seq(io.outs.asSeq.head(0)(0))
73+
// Combinational logic, but a maximum flight path of 4 elements
74+
val MAX_FLIGHT = 4
75+
io.lsbOuts := (io.lsbIns
76+
.drop(1)
77+
.reverse
78+
.sliding(MAX_FLIGHT, MAX_FLIGHT)
79+
.map { lsbs =>
80+
if (lsbs.length < MAX_FLIGHT) {
81+
lsbs
82+
} else {
83+
lsbs.dropRight(1) ++ Seq(RegNext(lsbs.last))
84+
}
85+
})
86+
.flatten
87+
.toSeq
88+
.reverse ++ Seq(io.outs.asSeq.head(0)(0))
7589
}
7690

7791
val ces = Seq.fill(height)(Seq.fill(width)(Module(new Element())))

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