Merge pull request #2803 from The-OpenROAD-Project-staging/synth-check

synth: Add check for unmapped cells; fix ihp-sg13g2

Author: maliberty

flow/platforms/ihp-sg13g2/cells_latch.v

@@ -6,3 +6,11 @@ module $_DLATCH_P_(input E, input D, output Q);
         );
 endmodule
 
+module $_DLATCH_N_(input E, input D, output Q);
+    sg13g2_dllrq_1 _TECHMAP_REPLACE_ (
+        .D(D),
+        .GATE_N(E),
+        .RESET_B(1'b1),
+        .Q(Q)
+        );
+endmodule

flow/scripts/synth.tcl

@@ -100,6 +100,9 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check
 
 tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
 
+# check the design is composed exclusively of target cells, and check for other problems
+check -assert -mapped
+
 # Write synthesized design
 write_verilog -noexpr -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v
 # One day a more sophisticated synthesis will write out a modified