Support new optimization flows

1) SYNTH_OPT_HIER to enable optimization across hier boundaries
2) SKIP_VT_SWAP to disable new VT swap opto
3) SKIP_REPAIR_TIE_FANOUT to skip tie fanout repair

Signed-off-by: Cho Moon <[email protected]>

Author: precisionmoon

flow/scripts/floorplan.tcl

@@ -95,21 +95,23 @@ if { [env_var_exists_and_non_empty MAKE_TRACKS] } {
 
 source_env_var_if_exists FOOTPRINT_TCL
 
-# This needs to come before any call to remove_buffers.  You could have one
-# tie driving multiple buffers that drive multiple outputs.
-# Repair tie lo fanout
-puts "Repair tie lo fanout..."
-set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
-set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
-
-# Repair tie hi fanout
-puts "Repair tie hi fanout..."
-set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
-set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
+if { ![env_var_equal SKIP_REPAIR_TIE_FANOUT 1] } {
+  # This needs to come before any call to remove_buffers.  You could have one
+  # tie driving multiple buffers that drive multiple outputs.
+  # Repair tie lo fanout
+  puts "Repair tie lo fanout..."
+  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
+  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
+  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
+  
+  # Repair tie hi fanout
+  puts "Repair tie hi fanout..."
+  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
+  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
+  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
+}
 
 if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
   estimate_parasitics -placement
@@ -121,7 +123,7 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
   remove_buffers
 } else {
   # Skip clone & split
-  set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer"
+  set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer,vt_swap"
   set ::env(SKIP_LAST_GASP) 1
   repair_timing_helper -setup
 }

flow/scripts/synth.tcl

@@ -28,6 +28,9 @@ if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } {
   set synth_full_args [concat $synth_full_args \
     "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
 }
+if { [env_var_exists_and_non_empty SYNTH_OPT_HIER] } {
+  set synth_full_args [concat $synth_full_args -hieropt]
+}
 
 if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
   # Perform standard coarse-level synthesis script, flatten right away

flow/scripts/util.tcl

@@ -25,6 +25,7 @@ proc repair_timing_helper { args } {
   append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0
   append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0
   append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0
+  append_env_var additional_args SKIP_VT_SWAP -skip_vt_swap 0
   append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   log_cmd repair_timing {*}$additional_args
 }

flow/scripts/variables.yaml

@@ -553,6 +553,13 @@ SKIP_PIN_SWAP:
     - cts
     - floorplan
     - grt
+SKIP_VT_SWAP:
+  description: >
+    Do not perform VT swap to improve QoR (default: do VT swap).
+  stages:
+    - cts
+    - floorplan
+    - grt
 REMOVE_CELLS_FOR_EQY:
   description: >
     String patterns directly passed to write_verilog -remove_cells <> for
@@ -565,6 +572,11 @@ SKIP_CTS_REPAIR_TIMING:
     architectural exploration or when getting CI up and running.
   stages:
     - cts
+SKIP_REPAIR_TIE_FANOUT:
+  description: >
+    Skip repair_tie_fanout at floorplan step.
+  stages:
+    - floorplan
 MIN_ROUTING_LAYER:
   description: |
     The lowest metal layer name to be used in routing.
@@ -712,6 +724,11 @@ SYNTH_HIER_SEPARATOR:
   description: |
     Separator used for the synthesis flatten stage.
   default: .
+SYNTH_OPT_HIER:
+  description: |
+    Optimize constants across hierarchical boundaries.
+  stages:
+    - synth
 VERILOG_TOP_PARAMS:
   description: |
     Apply toplevel params (if exist).