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louiiclouiic
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Merge branch 'The-OpenROAD-Project:master' into mab_0509
2 parents efd145c + df9a442 commit d0266ef

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25 files changed

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-3132
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‎flow/Makefile‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,8 @@
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# DESIGN_CONFIG=./designs/intel22/aes/config.mk
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# DESIGN_CONFIG=./designs/gf180/aes/config.mk
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# DESIGN_CONFIG=./designs/gf180/ibex/config.mk
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# DESIGN_CONFIG=./designs/gf180/jpeg/config.mk
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#
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# Default design
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DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk
@@ -656,11 +658,10 @@ finish: $(LOG_DIR)/6_report.log \
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$(RESULTS_DIR)/6_final.v \
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$(RESULTS_DIR)/6_final.sdc \
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$(GDS_FINAL_FILE)
659-
$(MAKE) elapsed
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-@$(UTILS_DIR)/genElapsedTime.py -d "$(LOG_DIR)"
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.PHONY:
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elapsed:
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@printf "%-25s %10s\n" Log "Elapsed seconds"
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-@$(UTILS_DIR)/genElapsedTime.py -d "$(LOG_DIR)"
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# ==============================================================================

‎flow/designs/asap7/mock-array-big/Element/io.tcl‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -37,17 +37,18 @@ set assignments [list \
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proc zip {list1 list2} {
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set result {}
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set length [llength $list1]
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set skip [expr [llength $list2] - [llength $list1]]
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for {set i 0} {$i < $length} {incr i} {
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lappend result [lindex $list1 $i] [lindex $list2 $i]
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lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i]
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}
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return $result
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}
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foreach {direction direction2 names} $assignments {
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set mirrored [zip {*}$names]
49-
set_io_pin_constraint -region $direction:* -pin_names [lindex $names 0]
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set_io_pin_constraint -group -order -pin_names [lindex $names 0]
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set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1]
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set_io_pin_constraint -group -order -pin_names [lindex $names 1]
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set_io_pin_constraint -mirrored_pins $mirrored
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}
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‎flow/designs/asap7/swerv_wrapper/metadata-base-ok.json‎

Lines changed: 247 additions & 219 deletions
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‎flow/designs/asap7/swerv_wrapper/rules-base.json‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,11 @@
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 53465,
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"value": 53272,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 213634,
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"value": 213024,
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"compare": "<="
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},
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"detailedplace__design__violations": {
@@ -36,7 +36,7 @@
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 9288,
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"value": 9262,
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"compare": "<="
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},
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"globalroute__timing__clock__slack": {
@@ -48,23 +48,23 @@
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 2098181,
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"value": 1991530,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"value": 0,
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"value": 1,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": 0.0,
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"compare": ">="
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},
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"finish__design__instance__area": {
63-
"value": 55030,
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"value": 53758,
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"compare": "<="
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},
6666
"finish__timing__drv__max_slew_limit": {
67-
"value": -2.71,
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"value": -2.53,
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"compare": ">="
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},
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"finish__timing__drv__max_fanout_limit": {

‎flow/designs/gf180/ibex/autotuner.json‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
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{
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"_SDC_FILE_PATH": "constraint.sdc",
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"_SDC_CLK_PERIOD": {
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"type": "float",
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"minmax": [
6+
1.0,
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15.155
8+
],
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"step": 0
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},
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"CORE_UTILIZATION": {
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"type": "int",
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"minmax": [
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20,
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100
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],
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"step": 1
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},
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"CORE_ASPECT_RATIO": {
20+
"type": "float",
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"minmax": [
22+
0.5,
23+
2.0
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],
25+
"step": 0
26+
},
27+
"CORE_MARGIN": {
28+
"type": "int",
29+
"minmax": [
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2,
31+
2
32+
],
33+
"step": 0
34+
},
35+
"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
36+
"type": "int",
37+
"minmax": [
38+
0,
39+
5
40+
],
41+
"step": 1
42+
},
43+
"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
44+
"type": "int",
45+
"minmax": [
46+
0,
47+
5
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],
49+
"step": 1
50+
},
51+
"_FR_LAYER_ADJUST": {
52+
"type": "float",
53+
"minmax": [
54+
0.1,
55+
0.7
56+
],
57+
"step": 0
58+
},
59+
"PLACE_DENSITY_LB_ADDON": {
60+
"type": "float",
61+
"minmax": [
62+
0.0,
63+
0.99
64+
],
65+
"step": 0
66+
},
67+
"_PINS_DISTANCE": {
68+
"type": "int",
69+
"minmax": [
70+
1,
71+
4
72+
],
73+
"step": 1
74+
},
75+
"CTS_CLUSTER_SIZE": {
76+
"type": "int",
77+
"minmax": [
78+
10,
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200
80+
],
81+
"step": 1
82+
},
83+
"CTS_CLUSTER_DIAMETER": {
84+
"type": "int",
85+
"minmax": [
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20,
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400
88+
],
89+
"step": 1
90+
},
91+
"_FR_FILE_PATH": "",
92+
"_FR_GR_OVERFLOW": {
93+
"type": "int",
94+
"minmax": [
95+
1,
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1
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],
98+
"step": 0
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}
100+
}

‎flow/designs/gf180/ibex/config.mk‎

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Original file line numberDiff line numberDiff line change
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export DESIGN_NICKNAME = ibex
2+
export DESIGN_NAME = ibex_core
3+
export PLATFORM = gf180
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5+
export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \
6+
./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
7+
./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
8+
./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \
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./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \
10+
./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \
11+
./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
12+
./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \
13+
./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
14+
./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
15+
./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
16+
./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
17+
./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \
18+
./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
19+
./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
20+
./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
21+
./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
22+
./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
23+
./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
24+
./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
25+
./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
26+
./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
27+
./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
28+
./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
29+
./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
30+
./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
31+
./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
32+
./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
33+
./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
34+
./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
35+
./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
36+
./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
37+
./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
38+
./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
39+
./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
40+
./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
41+
./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v
42+
43+
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
44+
45+
export CORE_UTILIZATION = 45
46+
export PLACE_DENSITY_LB_ADDON = 0.1

‎flow/designs/gf180/ibex/constraint.sdc‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
current_design ibex_core
2+
3+
set clk_name core_clock
4+
set clk_port_name clk_i
5+
set clk_period 15.0
6+
set clk_io_pct 0.2
7+
8+
set clk_port [get_ports $clk_port_name]
9+
10+
create_clock -name $clk_name -period $clk_period $clk_port
11+
12+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
13+
14+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
15+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_false_path -from [get_ports {rst_ni}]

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