Use estimates for ungrouping decisions

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/Makefile

@@ -178,9 +178,6 @@ include $(PLATFORM_DIR)/config.mk
 # is no way to escape space in defaults.py and get "foreach" to work.
 $(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
 
-# Enables hierarchical yosys
-export SYNTH_STATS = $(RESULTS_DIR)/synth_stats.txt
-export SYNTH_STATS_SCRIPT = $(SCRIPTS_DIR)/synth_stats.tcl
 # If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here
 export MAX_UNGROUP_SIZE ?= 0
 
@@ -454,13 +451,6 @@ memory:
 
 export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
 export SYNTH_MEMORY_MAX_BITS ?= 4096
-
-.PHONY: do-yosys-stats
-do-yosys-stats:
-	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
-	(export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \
-	$(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_STATS_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_stats.log)
-
 export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
 
 $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
@@ -487,7 +477,7 @@ $(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES)
 	$(UNSET_AND_MAKE) do-yosys-canonicalize
 
 $(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil
-	$(UNSET_AND_MAKE) do-yosys-stats do-yosys
+	$(UNSET_AND_MAKE) do-yosys
 
 .PHONY: do-synth
 do-synth:

flow/scripts/synth.tcl

@@ -2,36 +2,41 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 
 hierarchy -check -top $::env(DESIGN_NAME)
 
-set ungroup_threshold 0
-if { $::env(MAX_UNGROUP_SIZE) > 0 } {
-  set ungroup_threshold $::env(MAX_UNGROUP_SIZE)
-  puts "Ungroup modules of size greater than $ungroup_threshold"
-}
-
-set fp [open $::env(SYNTH_STATS) r]
-while {[gets $fp line] != -1} {
-    set fields [split $line " "]
-    set area [lindex $fields 0]
-    set module_name [lindex $fields 1]
-
-    if {[expr $area > $ungroup_threshold]} {
-      puts "Keeping module $module_name (area: $area)"
-      select -module $module_name
-      setattr -mod -set keep_hierarchy 1
-      select -clear
-    } else {
-      puts "Flattening module $module_name (area: $area)"
-    }
-}
-close $fp
-
 if { [env_var_equals SYNTH_GUT 1] } {
   # /deletes all cells at the top level, which will quickly optimize away
   # everything else, including macros.
   delete $::env(DESIGN_NAME)/c:*
 }
 
-synthesize_check mem $::env(SYNTH_FULL_ARGS)
+if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
+  # Perform standard coarse-level synthesis script, flatten right away
+  # (-flatten part of $synth_args per default)
+  synth -run :fine {*}$::env(SYNTH_FULL_ARGS)
+} else {
+  # Perform standard coarse-level synthesis script,
+  # defer flattening until we have decided what hierarchy to keep
+  synth -run :fine
+
+  if {[env_var_exists_and_non_empty MAX_UNGROUP_SIZE]} {
+    set ungroup_threshold $::env(MAX_UNGROUP_SIZE)
+    puts "Ungroup modules below estimated size of $ungroup_threshold instances"
+
+    convert_liberty_areas
+    keep_hierarchy -min_cost $ungroup_threshold
+  } else {
+    keep_hierarchy
+  }
+
+  # Re-run coarse-level script, this time do pass -flatten
+  synth -run coarse:fine {*}$::env(SYNTH_FULL_ARGS)
+}
+
+json -o $::env(RESULTS_DIR)/mem.json
+# Run report and check here so as to fail early if this synthesis run is doomed
+exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
+synth -top $::env(DESIGN_NAME) -run fine: {*}$::env(SYNTH_FULL_ARGS)
+# Get rid of indigestibles
+chformal -remove
 
 # rename registers to have the verilog register name in its name
 # of the form \regName$_DFF_P_. We should fix yosys to make it the reg name.

flow/scripts/synth_preamble.tcl

@@ -38,8 +38,9 @@ foreach file $::env(VERILOG_FILES) {
 
 # Read standard cells and macros as blackbox inputs
 # These libs have their dont_use properties set accordingly
-read_liberty -overwrite -lib {*}$::env(DONT_USE_LIBS)
-read_liberty -overwrite -unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS)
+read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(DONT_USE_LIBS)
+read_liberty -overwrite -setattr liberty_cell \
+  -unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS)
 
 # Apply toplevel parameters (if exist)
 if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {
@@ -108,13 +109,30 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)"
 puts $constr "set_load $::env(ABC_LOAD_IN_FF)"
 close $constr
 
-proc synthesize_check {report synth_args} {
-  # Generic synthesis
-  log_cmd synth -top $::env(DESIGN_NAME) -run :fine {*}$synth_args
-  json -o $::env(RESULTS_DIR)/$report.json
-  # Run report and check here so as to fail early if this synthesis run is doomed
-  exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/$report.json
-  synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args
-  # Get rid of indigestibles
-  chformal -remove
+proc convert_liberty_areas {} {
+  cellmatch -derive_luts =A:liberty_cell
+  # find a reference nand2 gate
+  set found_cell ""
+  set found_cell_area ""
+  foreach cell [tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m] {
+    if {! [rtlil::has_attr -mod $cell area]} {
+      puts "Cell $cell missing area information"
+      continue
+    }
+    set area [rtlil::get_attr -string -mod $cell area]
+    if {$found_cell == "" || [expr $area < $found_cell_area]} {
+      set found_cell $cell
+      set found_cell_area $area
+    }
+  }
+  if {$found_cell == ""} {
+    error "reference nand2 cell not found"
+  }
+
+  # convert the area on all Liberty cells to a gate number equivalent
+  foreach box [tee -q -s result.string select -list-mod =A:area =A:liberty_cell %i] {
+    set area [rtlil::get_attr -mod -string $box area]
+    set gate_eq [expr int($area / $found_cell_area)]
+    rtlil::set_attr -mod -uint $box gate_cost_equivalent $gate_eq
+  }
 }