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Merge pull request #1311 from The-OpenROAD-Project-staging/ma@update2
Mock-array - power grid fixed + new constraint
2 parents d7c9924 + 2918fc0 commit d14bf69

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5 files changed

+281
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Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,27 @@
11
set sdc_version 2.0
22

3-
set clk_period 1000
4-
create_clock [get_ports clock] -period $clk_period -waveform [list 0 [expr $clk_period/2]]
3+
set clk_period 500
54

65
set clk_name clock
76
set clk_port_name clock
8-
set clk_io_pct 0.2
7+
set clk_in_pct 0.75
8+
set clk_o1_pct 0.2
9+
set clk_o2_pct 0.75
910

10-
set clk_port [get_ports $clk_port_name]
11+
create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk_port_name]
12+
set_clock_uncertainty 20 [get_clocks $clk_name]
13+
14+
create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
15+
set_clock_uncertainty 20 [get_clocks ${clk_name}_vir]
16+
set_clock_latency 250 [get_clocks ${clk_name}_vir] ;# Matching real clock latency
1117

18+
set clk_port [get_ports $clk_port_name]
1219
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
20+
set non_reg_outputs [lsearch -inline -all -not -exact [all_outputs] [get_ports io_lsbs_*]]
21+
22+
set_input_delay [expr $clk_period * $clk_in_pct] -clock ${clk_name}_vir $non_clock_inputs
23+
set_output_delay [expr $clk_period * $clk_o1_pct] -clock ${clk_name}_vir $non_reg_outputs
24+
set_output_delay [expr $clk_period * $clk_o2_pct] -clock ${clk_name}_vir [get_ports io_lsbs_*]
1325

14-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
15-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
26+
set_max_transition 300 [current_design]
27+
set_max_transition 100 -clock_path [all_clocks]

flow/designs/asap7/mock-array/defaults.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
# current unit is configured as 2.16 which is on the routing grid for M5
44

55
# table of Elements - (rows cols width height pitch_x pitch_y)
6-
export MOCK_ARRAY_TABLE ?= 8 8 20 20 20 21
6+
export MOCK_ARRAY_TABLE ?= 8 8 20 20 20 22
77

88
# Element'd data width
99
export MOCK_ARRAY_DATAWIDTH ?= 64

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