Merge remote-tracking branch 'origin/master' into ng45_refactor

Signed-off-by: Ravi Varadarajan <[email protected]>

Author: ravi-varadarajan

flow/designs/asap7/mock-array-big/Element/config.mk

@@ -23,8 +23,6 @@ export PDN_TCL = designs/asap7/mock-array-big/Element/pdn.tcl
 # to the ring and stipe
 export MAX_ROUTING_LAYER = M5
 
-export PRIVATE_DIR=designs/asap7/mock-array-big
-
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 3 iterations were needed for 0
 # violations.

flow/designs/asap7/mock-array-big/Element/constraints.sdc

@@ -8,6 +8,8 @@ set clk_period 8000
 
 set clk_port [get_ports $clk_port_name]
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
+set_clock_uncertainty -setup 20.0 [get_clocks $clk_name]
+set_clock_uncertainty -hold 20.0 [get_clocks $clk_name]
 
 # io_ins_x -> REG_x
 set_input_delay -clock $clk_name -min [expr $clk_period / 2] [get_ports {io_ins_*}]
@@ -38,3 +40,10 @@ set_output_delay -clock $clk_name -max $max_delay [get_ports {io_lsbOuts_7}]
 #  and do not need to be constrained.
 set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
 set_false_path -from $non_clk_inputs -to [all_outputs]
+
+# Set driving cell and load capacitance explicitly to ensure timing results are sufficiently pessimistic
+set_driving_cell [all_inputs] -lib_cell BUFx2_ASAP7_75t_R
+# Assuming the load on each output is a BUFx2_ASAP7_75t_R, we pessimistically use 3 times the highest input
+#  pin capacitance for this cell, which is 0.577042.
+#  See platforms/asap7/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz, line 1223.
+set_load -pin_load 1.731126 [all_outputs]

flow/designs/asap7/mock-array-big/config.mk

@@ -26,7 +26,10 @@ export IO_CONSTRAINTS = designs/asap7/mock-array-big/io.tcl
 export PDN_TCL = designs/asap7/mock-array-big/pdn.tcl
 export TNS_END_PERCENT       = 100
 
-export PRIVATE_DIR=designs/asap7/mock-array-big
+# Target to force generation of Verilog per user settings
+#   MOCK_ARRAY_WIDTH and MOCK_ARRAY_HEIGHT
+verilog:
+	./designs/asap7/mock-array-big/verilog.sh
 
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 3 iterations were needed for 0

flow/designs/asap7/mock-array-big/metadata-base-ok.json

@@ -8,11 +8,11 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 12786,
+        "value": 12493,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 12574,
+        "value": 3464,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -32,11 +32,11 @@
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 547,
+        "value": 151,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 548,
+        "value": 151,
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
@@ -48,7 +48,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 45359,
+        "value": 22167,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -60,7 +60,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 12788,
+        "value": 12494,
         "compare": "<="
     },
     "finish__timing__drv__max_slew_limit": {