Merge branch 'master' into test-nangate45_regenerate_rams

AcKoucher · AcKoucher · commit d2c7db57db33 · 2023-11-09T10:04:19.000-03:00
diff --git a/flow/Makefile b/flow/Makefile
@@ -839,7 +839,6 @@ skip_resize: $(RESULTS_DIR)/3_3_place_gp.odb
 skip_cts: $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/3_place.sdc
 	# mock all intermediate results
 	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/4_1_cts.odb
-	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/4_2_cts_fillcell.odb
 	cp $(RESULTS_DIR)/3_place.sdc $(RESULTS_DIR)/4_cts.sdc
 	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/4_cts.odb
 
@@ -1078,7 +1077,7 @@ handoff : all_defs all_verilog
 
 .PHONY: print-%
 # Print any variable, for instance: make print-DIE_AREA
-print-%  : ; @echo $* = $($*)
+print-%  : ; @echo "$* = $($*)"
 
 .PHONY: test-unset-and-make-%
 test-unset-and-make-%: ; $(UNSET_AND_MAKE) $*
diff --git a/flow/designs/gf12/aes/config.mk b/flow/designs/gf12/aes/config.mk
@@ -18,3 +18,4 @@ else
 export DESIGN_TYPE = CELL_NODEN
 endif
 
+export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
@@ -34,3 +34,5 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
+
+export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/gf12/ariane/constraint.sdc b/flow/designs/gf12/ariane/constraint.sdc
diff --git a/flow/designs/gf12/ariane/constraint_hier.sdc b/flow/designs/gf12/ariane/constraint_hier.sdc
diff --git a/flow/designs/gf12/ca53/config.mk b/flow/designs/gf12/ca53/config.mk
@@ -58,3 +58,4 @@ export DESIGN_TYPE = CELL_NODEN
 endif
 
 export SKIP_PIN_SWAP          = 1
+export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/gf12/ca53/config_mpl2.mk b/flow/designs/gf12/ca53/config_mpl2.mk
@@ -67,3 +67,5 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
+
+export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/gf55/aes/metadata-base-ok.json b/flow/designs/gf55/aes/metadata-base-ok.json
diff --git a/flow/designs/gf55/aes/rules-base.json b/flow/designs/gf55/aes/rules-base.json
@@ -40,7 +40,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 154782,
+        "value": 178042,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
diff --git a/flow/designs/intel16/gcd/metadata-base-ok.json b/flow/designs/intel16/gcd/metadata-base-ok.json
diff --git a/flow/designs/intel16/gcd/rules-base.json b/flow/designs/intel16/gcd/rules-base.json
@@ -36,11 +36,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -352.01,
+        "value": -9.79,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 179,
+        "value": 227,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
@@ -52,7 +52,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -37.98,
+        "value": -10.0,
         "compare": ">="
     }
 }
diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk
@@ -32,3 +32,5 @@ export MACRO_PLACE_CHANNEL = 20 20
 
 export PLACE_DENSITY_LB_ADDON = 0.10
 export TNS_END_PERCENT        = 100
+
+export SKIP_INCREMENTAL_REPAIR = 1
diff --git a/flow/designs/nangate45/tinyRocket/metadata-base-ok.json b/flow/designs/nangate45/tinyRocket/metadata-base-ok.json
diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json
@@ -36,7 +36,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.14,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/sky130hs/riscv32i/config.mk b/flow/designs/sky130hs/riscv32i/config.mk
@@ -10,3 +10,5 @@ export PLACE_DENSITY_LB_ADDON = 0.2
 # many east pins cause global routing congestion
 export PLACE_PINS_ARGS=-min_distance 6 -min_distance_in_tracks
 export TNS_END_PERCENT = 100
+
+export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
diff --git a/flow/designs/sky130hs/riscv32i/fastroute.tcl b/flow/designs/sky130hs/riscv32i/fastroute.tcl
@@ -0,0 +1,3 @@
+set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.15
+
+set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk
@@ -39,6 +39,19 @@ export TC_LIB_FILES           = $(PLATFORM_DIR)/lib/asap7sc7p5t_AO_RVT_TT_nldm_2
 
 export TC_DFF_LIB_FILE        = $(PLATFORM_DIR)/lib/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib
 
+ifdef CLUSTER_FLOPS
+  # Add the multi-bit FF for clustering.  These are single corner libraries.
+  export ADDITIONAL_LIBS     += $(PLATFORM_DIR)/lib/asap7sc7p5t_DFFHQNH2V2X_RVT_TT_nldm_FAKE.lib \
+                                $(PLATFORM_DIR)/lib/asap7sc7p5t_DFFHQNV2X_RVT_TT_nldm_FAKE.lib \
+                                $(PLATFORM_DIR)/lib/asap7sc7p5t_DFFHQNV4X_RVT_TT_nldm_FAKE.lib
+
+  export ADDITIONAL_LEFS     += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \
+                                $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef \
+                                $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV4X.lef
+endif
+
+
+
 export BC_TEMPERATURE          = 25C
 export TC_TEMPERATURE          = 0C
 export WC_TEMPERATURE          = 100C
diff --git a/flow/platforms/sky130hd/fastroute.tcl b/flow/platforms/sky130hd/fastroute.tcl
@@ -1,4 +1,4 @@
-set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.3
+set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.2
 
 set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
diff --git a/flow/platforms/sky130hs/fastroute.tcl b/flow/platforms/sky130hs/fastroute.tcl
@@ -1,3 +1,3 @@
-set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.3
+set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.2
 
 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl
@@ -1,16 +1,29 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 6_final.odb 6_final.sdc "Starting generation of abstract views"
 
-read_spef $::env(RESULTS_DIR)/6_final.spef
-set_propagated_clock [all_clocks]
+set stem [expr {[info exists ::env(ABSTRACT_SOURCE)] ? $::env(ABSTRACT_SOURCE) : "6_final"}]
+
+set design_stage [lindex [split [file tail $stem] "_"] 0]
+
+load_design $stem.odb $stem.sdc "Starting generation of abstract views"
+
+if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} {
+  read_spef $::env(RESULTS_DIR)/$stem.spef
+} elseif {$design_stage >= 3} {
+  puts "Estimating parasitics"
+  estimate_parasitics -placement
+}
+
+if {$design_stage >= 4} {
+  set_propagated_clock [all_clocks]
+}
 
 puts "Starting generation of abstract views"
 write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib
 write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef
 
 if {[info exist ::env(CDL_FILES)]} {
   cdl read_masters $::env(CDL_FILES)
-  cdl out $::env(RESULTS_DIR)/6_final.cdl
+  cdl out $::env(RESULTS_DIR)/$stem.cdl
 }
 
 if {![info exists standalone] || $standalone} {
diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl
@@ -52,6 +52,11 @@ global_placement -density $place_density \
 
 estimate_parasitics -placement
 
+if {[info exist ::env(CLUSTER_FLOPS)]} {
+  cluster_flops
+  estimate_parasitics -placement
+}
+
 source $::env(SCRIPTS_DIR)/report_metrics.tcl
 report_metrics "global place" false false
 
diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl
@@ -30,12 +30,45 @@ global_route -guide_file $env(RESULTS_DIR)/route.guide \
 set_placement_padding -global \
     -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
     -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
-repair_antennas -iterations 5
-check_placement -verbose
 
 set_propagated_clock [all_clocks]
 estimate_parasitics -global_routing
 
+if {[info exist env(DONT_USE_CELLS)]} {
+  set_dont_use $::env(DONT_USE_CELLS)
+}
+
+source $env(SCRIPTS_DIR)/report_metrics.tcl
+
+if { ![info exists ::env(SKIP_INCREMENTAL_REPAIR)] } {
+  report_metrics "global route pre repair design"
+
+  # Repair design using global route parasitics
+  puts "Perform buffer insertion..."
+  repair_design
+  report_metrics "global route post repair design"
+
+  # Running DPL to fix overlapped instances
+  # Run to get modified net by DPL
+  global_route -start_incremental
+  detailed_placement
+  # Route only the modified net by DPL
+  global_route -end_incremental -congestion_report_file $env(REPORTS_DIR)/congestion_post_repair_design.rpt
+
+  # Repair timing using global route parasitics
+  puts "Repair setup and hold violations..."
+  estimate_parasitics -global_routing
+  repair_timing
+  report_metrics "global route post repair timing"
+
+  # Running DPL to fix overlapped instances
+  # Run to get modified net by DPL
+  global_route -start_incremental
+  detailed_placement
+  # Route only the modified net by DPL
+  global_route -end_incremental -congestion_report_file $env(REPORTS_DIR)/congestion_post_repair_timing.rpt
+}
+
 if { [info exists ::env(RECOVER_POWER)] } {
   puts "Downsizing/switching to higher Vt  for non critical gates for power recovery"
   puts "Percent of paths optimized $::env(RECOVER_POWER)"  
@@ -48,14 +81,17 @@ if { [info exists ::env(RECOVER_POWER)] } {
   report_power
 }
 
-source $env(SCRIPTS_DIR)/report_metrics.tcl
-report_metrics "global route"
-
 puts "\n=========================================================================="
 puts "check_antennas"
 puts "--------------------------------------------------------------------------"
+
+repair_antennas -iterations 5
+check_placement -verbose
 check_antennas -report_file $env(REPORTS_DIR)/antenna.log -report_violating_nets
 
+estimate_parasitics -global_routing
+report_metrics "global route"
+
 # Write SDC to results with updated clock periods that are just failing.
 # Use make target update_sdc_clock to install the updated sdc.
 source [file join $env(SCRIPTS_DIR) "write_ref_sdc.tcl"]
diff --git a/flow/util/def2stream.py b/flow/util/def2stream.py
@@ -47,20 +47,6 @@ def read_cfg():
 
 #match a line like:
 # - LAYER M2 + MASK 2 + OPC RECT ( 3000 3000 ) ( 5000 5000 ) ;
-#rect_pat = re.compile(r'''
-# \s*\-\ LAYER\ (?P<layer>\S+)  # The layer name
-#  (?:                           # Non-capturing group
-#  \s+\+\ MASK\ (?P<mask>\d+)    # Mask, None if absent
-#  )?
-#  (?P<opc>                      # OPC, None if absent
-#  \s+\+\ OPC
-#  )?
-#  \s+RECT\
-#   \(\ (?P<xlo>\d+)\ (?P<ylo>\d+)\ \)\   # rect lower-left pt
-#  \(\ (?P<xhi>\d+)\ (?P<yhi>\d+)\ \)\ ; # rect upper-right pt
-    #  ''',
-#                  re.VERBOSE)
-
 rect_pat = re.compile(r'''
   \s*\-\ LAYER\ (?P<layer>\S+)  # The layer name
   (?:                           # Non-capturing group
@@ -124,13 +110,9 @@ def read_fills(top):
 for i in main_layout.each_cell():
   print("[INFO] '{0}'".format(i.name))
 
-print("[INFO] Reading DEF  ...")
+print("[INFO] Reading DEF ...")
 main_layout.read(in_def, layoutOptions)
 
-print("[INFO] Reporting cells after loading DEF ...")
-for i in main_layout.each_cell():
-  print("[INFO] '{0}'".format(i.name))
-
 # Clear cells
 top_cell_index = main_layout.cell(design_name).cell_index()
 
diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py
@@ -30,7 +30,7 @@ def print_log_dir_times(logdir):
     print(logdir)
 
     # Loop on all log files in the directory
-    for f in sorted(pathlib.Path(logdir).glob('**/[0-9]_*.log')):
+    for f in sorted(pathlib.Path(logdir).glob('**/*.log')):
         # Extract Elapsed Time line from log file
         with open(str(f)) as logfile:
             found = False
diff --git a/tools/OpenROAD b/tools/OpenROAD
@@ -1 +1 @@
-Subproject commit 6719c92e6ea92f0dc889c1f6806efd967c0c665e
+Subproject commit 2bdae1c13b8c6387644f12f760254f472b04f4e7

Original file line number	Diff line number	Diff line change
`@@ -18,3 +18,4 @@ else`
`18`	`18`	`export DESIGN_TYPE = CELL_NODEN`
`19`	`19`	`endif`
`20`	`20`
	`21`	`+export SKIP_INCREMENTAL_REPAIR = 1`
Original file line number	Diff line number	Diff line change
`@@ -58,3 +58,4 @@ export DESIGN_TYPE = CELL_NODEN`
`58`	`58`	`endif`
`59`	`59`
`60`	`60`	`export SKIP_PIN_SWAP = 1`
	`61`	`+export SKIP_INCREMENTAL_REPAIR = 1`