mock-array-big: Prettier verilog

Signed-off-by: Jake Taylor <[email protected]>

Author: yupferris

flow/designs/asap7/mock-array-big/configure.sh

@@ -10,4 +10,4 @@ cd $DIR
 cd ../../src/mock-array-big
 
 sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
-     "test:runMain GenerateMockArray --width ${MOCK_ARRAY_WIDTH:-8} --height ${MOCK_ARRAY_HEIGHT:-8} --dataWidth ${MOCK_ARRAY_DATAWIDTH:-8} -- --emit-modules verilog --target-dir ."
+     "test:runMain GenerateMockArray --width ${MOCK_ARRAY_WIDTH:-8} --height ${MOCK_ARRAY_HEIGHT:-8} --dataWidth ${MOCK_ARRAY_DATAWIDTH:-8} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."

flow/designs/src/mock-array-big/Element.v

@@ -25,12 +25,6 @@ module Element(
   output       io_lsbOuts_6, // @[src/test/scala/MockArray.scala 50:9]
   output       io_lsbOuts_7 // @[src/test/scala/MockArray.scala 50:9]
 );
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-`endif // RANDOMIZE_REG_INIT
   reg [7:0] REG; // @[src/test/scala/MockArray.scala 61:56]
   reg [7:0] REG_1; // @[src/test/scala/MockArray.scala 61:56]
   reg [7:0] REG_2; // @[src/test/scala/MockArray.scala 61:56]
@@ -53,55 +47,4 @@ module Element(
     REG_2 <= io_ins_up; // @[src/test/scala/MockArray.scala 61:56]
     REG_3 <= io_ins_left; // @[src/test/scala/MockArray.scala 61:56]
   end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {1{`RANDOM}};
-  REG = _RAND_0[7:0];
-  _RAND_1 = {1{`RANDOM}};
-  REG_1 = _RAND_1[7:0];
-  _RAND_2 = {1{`RANDOM}};
-  REG_2 = _RAND_2[7:0];
-  _RAND_3 = {1{`RANDOM}};
-  REG_3 = _RAND_3[7:0];
-`endif // RANDOMIZE_REG_INIT
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
 endmodule