Merge remote-tracking branch 'origin/master' into secure-update-OR

Author: osamahammad21

flow/Makefile

@@ -783,12 +783,20 @@ $(RESULTS_DIR)/6_final.def: $(LOG_DIR)/6_report.log
 do-finish:
 	$(UNSET_AND_MAKE) do-6_1_fill do-6_1_fill.sdc do-6_final.sdc do-6_report elapsed
 
-# Skipping resize can be useful for mock abstracts
+.PHONY: skip_place
+skip_place: $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/2_floorplan.sdc
+	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_1_place_gp_skip_io.odb
+	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_2_place_iop.odb
+	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_3_place_gp.odb
+	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_4_place_resized.odb
+	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_5_place_dp.odb
+	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_place.odb
+	cp $(RESULTS_DIR)/2_floorplan.sdc $(RESULTS_DIR)/3_place.sdc
+
 .PHONY: skip_resize
 skip_resize: $(RESULTS_DIR)/3_3_place_gp.odb
 	cp $(RESULTS_DIR)/3_3_place_gp.odb $(RESULTS_DIR)/3_4_place_resized.odb
 
-# Skipping CTS can be useful to smoketest later stages.
 .PHONY: skip_cts
 skip_cts: $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/3_place.sdc
 	# mock all intermediate results
@@ -797,18 +805,24 @@ skip_cts: $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/3_place.sdc
 	cp $(RESULTS_DIR)/3_place.sdc $(RESULTS_DIR)/4_cts.sdc
 	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/4_cts.odb
 
-# Skipping route can be useful to create a mock abstract
 .PHONY: skip_route
 skip_route: $(RESULTS_DIR)/4_cts.odb $(RESULTS_DIR)/4_cts.sdc
 	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/5_1_grt.odb
 	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/5_2_route.odb
 	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/6_1_fill.odb
 	touch $(RESULTS_DIR)/6_final.spef
 
-# To create a mock abstract quickly, good enough to iterate quickly on
-# floorplanning and detailed route at higher levels, run:
+# A mock abstract is a fully or partially eviscerated macro. A mock
+# abstract can be useful when creating bug reports, previewing
+# macro placement, testing detailed routing, or other quick smoke-tests
+# at the top level.
+#
+# When creating a mock abstract, depending on what needs to be tested,
+# stages can be skipped.
+#
+# Leave out "skip_" targes as approperiate:
 #
-# make skip_resize skip_cts skip_route generate_abstract
+# make skip_place skip_cts skip_route generate_abstract
 .PHONY: generate_abstract
 generate_abstract: $(RESULTS_DIR)/6_final.gds $(RESULTS_DIR)/6_final.def  $(RESULTS_DIR)/6_final.v $(RESULTS_DIR)/6_final.sdc
 	$(UNSET_AND_MAKE) do-generate_abstract

flow/designs/asap7/mock-array/Element/config.mk

@@ -24,7 +24,7 @@ export DIE_AREA = $(shell \
 
 export IO_CONSTRAINTS         = designs/asap7/mock-array/Element/io.tcl
 
-export PDN_TCL                = designs/asap7/mock-array/Element/pdn.tcl
+export PDN_TCL                = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
 
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 3 iterations were needed for 0

flow/designs/asap7/mock-array/config.mk

@@ -3,7 +3,6 @@ include designs/asap7/mock-array/defaults.mk
 export DESIGN_NAME            = MockArray
 export DESIGN_NICKNAME        = mock-array
 
-export VERILOG_FILES_BLACKBOX = designs/src/mock-array/Element.v
 export VERILOG_FILES          = designs/src/mock-array/*.v
 
 export SDC_FILE               = designs/asap7/mock-array/constraints.sdc
@@ -32,7 +31,7 @@ export MACRO_PLACEMENT_TCL   = ./designs/asap7/mock-array/macro-placement.tcl
 
 export IO_CONSTRAINTS        = designs/asap7/mock-array/io.tcl
 
-export PDN_TCL               = designs/asap7/mock-array/pdn.tcl
+export PDN_TCL               = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl
 
 # Target to force generation of Verilog per user settings MOCK_ARRAY_TABLE (rows, cols)
 verilog:

flow/designs/asap7/mock-array/pdn.tcl

@@ -1,7 +1,6 @@
 export DESIGN_NAME            = SramBridge
 export DESIGN_NICKNAME        = SramBridge
 
-export VERILOG_FILES_BLACKBOX = designs/src/sram-64x16/SRAM2RW16x32.v
 export VERILOG_FILES = designs/src/sram-64x16/*.sv
 
 export SDC_FILE               = designs/asap7/sram-64x16/constraints.sdc

flow/designs/asap7/sram-64x16/config.mk

@@ -8,8 +8,6 @@ export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
 export BLOCKS = uart_rx
 
-export VERILOG_FILES_BLACKBOX = ./designs/src/uart-no-param/uart_rx.v
-
 export DIE_AREA = 0 0 430 430
 export CORE_AREA = 10 10 420 420
 

flow/designs/gf180/uart-blocks/config.mk

@@ -5,9 +5,11 @@ export PLATFORM    = sky130hd
 export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
 export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
-export CORE_UTILIZATION = 20 
+export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks
+
+export CORE_UTILIZATION = 20
 export CORE_ASPECT_RATIO = 1
 export CORE_MARGIN = 2
 
-export PLACE_DENSITY = 0.65
+export PLACE_DENSITY = 0.6
 export TNS_END_PERCENT = 100