synthesis: keep memory information on hierarchical synthesis

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/Makefile

@@ -461,6 +461,9 @@ do-synth-report:
 
 .PHONY: memory
 memory:
+	if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \
+		python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \
+	fi
 	python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json
 
 # ==============================================================================
@@ -516,7 +519,7 @@ $(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v
 
 .PHONY: clean_synth
 clean_synth:
-	rm -f $(RESULTS_DIR)/1_* $(RESULTS_DIR)/mem.json
+	rm -f $(RESULTS_DIR)/1_* $(RESULTS_DIR)/mem*.json
 	rm -f $(REPORTS_DIR)/synth_*
 	rm -f $(LOG_DIR)/1_*
 	rm -f $(SYNTH_STOP_MODULE_SCRIPT)

flow/scripts/synth.tcl

@@ -9,7 +9,7 @@ if { [env_var_equals SYNTH_GUT 1] } {
   delete $::env(DESIGN_NAME)/c:*
 }
 
-synthesize_check $::env(SYNTH_FULL_ARGS)
+synthesize_check mem $::env(SYNTH_FULL_ARGS)
 
 # rename registers to have the verilog register name in its name
 # of the form \regName$_DFF_P_. We should fix yosys to make it the reg name.

flow/scripts/synth_hier_report.tcl

@@ -9,7 +9,7 @@ proc write_keep_hierarchy {} {
 
   source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 
-  synthesize_check {}
+  synthesize_check mem_hierarchical {}
 
   if { [env_var_exists_and_non_empty ADDER_MAP_FILE] && [file isfile $::env(ADDER_MAP_FILE)] } {
     techmap -map $::env(ADDER_MAP_FILE)

flow/scripts/synth_preamble.tcl

@@ -107,12 +107,12 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)"
 puts $constr "set_load $::env(ABC_LOAD_IN_FF)"
 close $constr
 
-proc synthesize_check {synth_args} {
+proc synthesize_check {report synth_args} {
   # Generic synthesis
   log_cmd synth -top $::env(DESIGN_NAME) -run :fine {*}$synth_args
-  json -o $::env(RESULTS_DIR)/mem.json
+  json -o $::env(RESULTS_DIR)/$report.json
   # Run report and check here so as to fail early if this synthesis run is doomed
-  exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
+  exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/$report.json
   synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args
   # Get rid of indigestibles
   chformal -remove