Retire REMOVE_ABC_BUFFERS now it has no effect

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

docs/user/FlowVariables.md

@@ -182,7 +182,6 @@ configuration file.
 | <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| |
 | <a name="RCX_RULES"></a>RCX_RULES| RC Extraction rules file path.| |
 | <a name="RECOVER_POWER"></a>RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0|
-| <a name="REMOVE_ABC_BUFFERS"></a>REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| |
 | <a name="REMOVE_CELLS_FOR_EQY"></a>REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| |
 | <a name="REPAIR_PDN_VIA_LAYER"></a>REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| |
 | <a name="REPORT_CLOCK_SKEW"></a>REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1|
@@ -313,7 +312,6 @@ configuration file.
 - [PLACE_DENSITY](#PLACE_DENSITY)
 - [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
 - [PLACE_SITE](#PLACE_SITE)
-- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [RTLMP_AREA_WT](#RTLMP_AREA_WT)
 - [RTLMP_ARGS](#RTLMP_ARGS)

flow/designs/asap7/minimal/config.mk

@@ -19,5 +19,4 @@ export SKIP_REPORT_METRICS = 1
 
 # Faster build, remove these in your own config.mk
 export SKIP_CTS_REPAIR_TIMING = 1
-export REMOVE_ABC_BUFFERS = 1
 export SKIP_INCREMENTAL_REPAIR = 1

flow/designs/gf12/ariane/config.mk

@@ -32,5 +32,3 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
-
-export REMOVE_ABC_BUFFERS = 1

flow/designs/gf12/ariane133/config.mk

@@ -29,5 +29,3 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
-
-export REMOVE_ABC_BUFFERS = 1

flow/designs/gf12/swerv_wrapper/config.mk

@@ -35,5 +35,3 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
-
-export REMOVE_ABC_BUFFERS = 1

flow/designs/ihp-sg13g2/aes/config.mk

@@ -12,5 +12,3 @@ export PLACE_DENSITY = 0.65
 export TNS_END_PERCENT = 100
 
 export USE_FILL = 1
-
-export REMOVE_ABC_BUFFERS = 1

flow/designs/ihp-sg13g2/jpeg/config.mk

@@ -9,6 +9,3 @@ export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
 export CORE_UTILIZATION = 50
 export PLACE_DENSITY_LB_ADDON = 0.15
 export TNS_END_PERCENT = 100
-
-export REMOVE_ABC_BUFFERS = 1
-

flow/designs/sky130hd/aes/config.mk

@@ -16,7 +16,5 @@ export TNS_END_PERCENT = 100
 
 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
 
-export REMOVE_ABC_BUFFERS = 1
-
 export CTS_CLUSTER_SIZE = 20
 export CTS_CLUSTER_DIAMETER = 50

flow/designs/sky130hd/ibex/BUILD.bazel

@@ -7,7 +7,6 @@ orfs_flow(
         "CORE_UTILIZATION": "45",
         "PLACE_DENSITY_LB_ADDON": "0.25",
         "TNS_END_PERCENT": "100",
-        "REMOVE_ABC_BUFFERS": "1",
         "SYNTH_HDL_FRONTEND": "slang",
         "VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl",
         "CTS_CLUSTER_SIZE": "20",

flow/designs/sky130hd/ibex/config.mk

@@ -21,7 +21,5 @@ export TNS_END_PERCENT = 100
 
 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
 
-export REMOVE_ABC_BUFFERS = 1
-
 export CTS_CLUSTER_SIZE = 20
 export CTS_CLUSTER_DIAMETER = 50