Iterate on tightening

Tighten some more, relax density for sky130hs/jpeg (fails) and clock
period for asap7/mock-alu (constraint far off from solution).

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc

@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 750
+set clk_period 680
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc

@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 650
+set clk_period 600
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/mock-alu/constraints.sdc

@@ -1,6 +1,6 @@
 set clk_name clock
 set clk_port_name clock
-set clk_period 100
+set clk_period 300
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/riscv32i/constraint.sdc

@@ -2,7 +2,7 @@ current_design riscv_top
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 1160
+set clk_period 1000
 set clk_io_pct 0.125
 
 set clk_port [get_ports $clk_port_name]

flow/designs/sky130hs/ibex/constraint.sdc

@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name core_clock
 set clk_port_name clk_i
-set clk_period 8.0
+set clk_period 7.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/sky130hs/jpeg/config.mk

@@ -7,7 +7,7 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ABC_AREA = 1
 
-export CORE_UTILIZATION = 65
+export CORE_UTILIZATION = 50
 export CORE_ASPECT_RATIO = 1
 export CORE_MARGIN = 2