@@ -9,24 +9,41 @@ export VERILOG_FILES += $(realpath ./designs/src/$(DESIGN_NICKNAME)/rock
99export SDC_FILE = $(realpath ./designs/$(PLATFORM ) /$(DESIGN_NICKNAME ) /constraint.sdc)
1010export SYNTH_SDC_FILE = $(SDC_FILE )
1111
12- export CORE_UTILIZATION = 40
13- export CORE_ASPECT_RATIO = 1
14- export CORE_MARGIN = 5
1512export PLACE_DENSITY_LB_ADDON = 0.05
1613
14+ export IO_CONSTRAINTS = $(dir $(DESIGN_CONFIG ) ) /io.tcl
15+ export MACRO_PLACEMENT_TCL = $(dir $(DESIGN_CONFIG ) ) /macro-placement.tcl
16+
17+ export PDN_TCL = $(dir $(DESIGN_CONFIG ) ) /pdn.tcl
18+
19+ export CORE_AREA = 2.5 2.5 1397.5 1397.5
20+ export DIE_AREA = 0 0 1400 1400
21+
1722export BC_ADDITIONAL_LIBS += $(PLATFORM_DIR ) /lib/fakeram_256x128.lib \
1823 $(PLATFORM_DIR ) /lib/fakeram_256x64.lib \
1924 $(PLATFORM_DIR ) /lib/fakeram_32x46.lib \
2025 $(PLATFORM_DIR ) /lib/fakeram_512x8.lib \
2126 $(PLATFORM_DIR ) /lib/fakeram_64x20.lib \
22- $(PLATFORM_DIR ) /lib/fakeram_64x22.lib
27+ $(PLATFORM_DIR ) /lib/fakeram_64x22.lib \
28+ $(PLATFORM_DIR ) /lib/fakeregfile_32x46.lib \
29+ $(PLATFORM_DIR ) /lib/fakeregfile_64x64.lib \
30+ $(PLATFORM_DIR ) /lib/fakeregfile_128x64.lib
2331
2432export ADDITIONAL_LEFS += $(PLATFORM_DIR ) /lef/fakeram_256x128.lef \
2533 $(PLATFORM_DIR ) /lef/fakeram_256x64.lef \
2634 $(PLATFORM_DIR ) /lef/fakeram_32x46.lef \
2735 $(PLATFORM_DIR ) /lef/fakeram_512x8.lef \
2836 $(PLATFORM_DIR ) /lef/fakeram_64x20.lef \
29- $(PLATFORM_DIR ) /lef/fakeram_64x22.lef
37+ $(PLATFORM_DIR ) /lef/fakeram_64x22.lef \
38+ $(PLATFORM_DIR ) /lef/fakeregfile_32x46.lef \
39+ $(PLATFORM_DIR ) /lef/fakeregfile_64x64.lef \
40+ $(PLATFORM_DIR ) /lef/fakeregfile_128x64.lef
3041
3142
3243# export CACHED_NETLIST = $(realpath ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/MegaBoom.v)
44+
45+ export SYNTH_ARGS =-noshare
46+
47+
48+ export MIN_ROUTING_LAYER = M2
49+ export MAX_ROUTING_LAYER = M9
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