Merge remote-tracking branch 'origin/master' into secure-gpl-binSize-float

Author: gudeh

README.md

@@ -97,6 +97,16 @@ Document for detailed local build from sources and installation steps found [her
 - To watch ORFS flow tutorial videos, check
   [here](https://theopenroadproject.org/video).
 
+## Building from your own git repository
+
+ORFS supports hosting projects in your own git repository
+without the need to fork ORFS.
+
+To build from your own git repository:
+
+    cd /home/me/myproject
+    make --file=~/OpenROAD-flow-scripts/flow/Makefile DESIGN_CONFIG=somefolder/config.mk ...
+
 ## Citing this Work
 
 If you use this software in any published work, we would appreciate a citation!

flow/Makefile

@@ -123,7 +123,7 @@ SHELL          := /usr/bin/env bash
 #   location
 # - default is current install / clone directory
 ifeq ($(origin FLOW_HOME), undefined)
-FLOW_HOME := $(shell pwd)
+FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
 endif
 export FLOW_HOME
 

flow/designs/asap7/gcd-ccs/metadata-base-ok.json

@@ -1,34 +1,38 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 43.75,
+        "value": 54.33,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 51,
+        "value": 64,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 508,
+        "value": 639,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 45,
+        "value": 101,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
         "value": 44,
         "compare": "<="
     },
+    "globalroute__antenna_diodes_count": {
+        "value": 0,
+        "compare": "<="
+    },
     "detailedroute__route__wirelength": {
-        "value": 1251,
+        "value": 1712,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -39,24 +43,28 @@
         "value": 0,
         "compare": "<="
     },
+    "detailedroute__antenna_diodes_count": {
+        "value": 5,
+        "compare": "<="
+    },
     "finish__timing__setup__ws": {
-        "value": -64.03,
+        "value": -92.68,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 54,
+        "value": 75,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 41,
+        "value": 47,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -22.54,
+        "value": -38.48,
         "compare": ">="
     }
 }

flow/designs/asap7/gcd-ccs/rules-base.json

@@ -24,7 +24,7 @@ export DIE_AREA = $(shell \
 
 export IO_CONSTRAINTS         = designs/asap7/mock-array/Element/io.tcl
 
-export PDN_TCL                = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
+export PDN_TCL                = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl
 
 # Detailed routing should be easy, limit iterations
 export DETAILED_ROUTE_END_ITERATION ?= 6

flow/designs/asap7/mock-array/Element/config.mk

@@ -13,8 +13,8 @@ mkdir -p $OBJ_DIR
 mkdir -p $POST_DIR
 
 # Copy Verilog files used for simulation to post dir in the objects area
-cp $FLOW_HOME/results/asap7/mock-array/base/6_final.v $POST_DIR/MockArrayFinal.v
-cp $FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v $POST_DIR/MockArrayElement.v
+cp $RESULTS_DIR/6_final.v $POST_DIR/MockArrayFinal.v
+cp $RESULTS_DIR/../../mock-array_Element/base/6_final.v $POST_DIR/MockArrayElement.v
 
 # Run simulation and have Verilator write the output files to the objects area
 verilator -Wall --cc \
@@ -31,10 +31,10 @@ verilator -Wall --cc \
   $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \
   $PLATFORM_DIR/verilog/stdcell/dff.v \
   $PLATFORM_DIR/verilog/stdcell/empty.v \
-  $FLOW_HOME/results/asap7/mock-array/base/6_final.v \
-  $FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v \
+  $RESULTS_DIR/6_final.v \
+  $RESULTS_DIR/../../mock-array_Element/base/6_final.v \
   --exe \
-  $FLOW_HOME/designs/src/mock-array/simulate.cpp
+  $DESIGN_HOME/src/mock-array/simulate.cpp
 
 # Link the generated object files into the VMockArray executable
 make -j16 -C $OBJ_DIR -f VMockArray.mk

flow/designs/asap7/mock-array/simulate.sh

@@ -14,4 +14,4 @@ export MAX_ROUTING_LAYER = M4
 
 export PLACE_PINS_ARGS = -exclude left:* -exclude bottom:* -exclude top:* -min_distance 6 -min_distance_in_tracks
 
-export PDN_TCL                = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
+export PDN_TCL                = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl