Merge remote-tracking branch 'origin/master' into secure-HV-gate-cloning-default

* origin/master:
  update OR submodule
  mock-array: pipeline lsb does max four CEs before registering
  Update_ok
  Signed-off-by: louiic <[email protected]>
  Modify - clock constraint
  Signed-off-by: louiic <[email protected]>
  Modify - macro hallow for PDN gen can not be > macro's halo
  Modify - placement pitch of Element must be even for power on M6 to connect          to M5 -> M2/M1 on rows between Element
  ci: metrics update

Signed-off-by: Vitor Bandeira <[email protected]>

Author: vvbandeira

flow/designs/asap7/aes/metadata-base-ok.json

@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 2858,
+        "value": 2717,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
@@ -56,7 +56,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -46.45,
+        "value": -28.87,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -76,11 +76,11 @@
         "compare": ">="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 30,
+        "value": 17,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 10,
+        "value": 102,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {

flow/designs/asap7/aes/rules-base.json

@@ -1,15 +1,27 @@
 set sdc_version 2.0
 
-set clk_period 1000
-create_clock [get_ports clock] -period $clk_period -waveform [list 0 [expr $clk_period/2]]
+set clk_period 500
 
 set clk_name  clock
 set clk_port_name clock
-set clk_io_pct 0.2
+set clk_in_pct 0.75
+set clk_o1_pct 0.2
+set clk_o2_pct 0.75
 
-set clk_port [get_ports $clk_port_name]
+create_clock -name $clk_name       -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk_port_name]
+set_clock_uncertainty 20 [get_clocks $clk_name]
+
+create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
+set_clock_uncertainty  20 [get_clocks ${clk_name}_vir]
+set_clock_latency     250 [get_clocks ${clk_name}_vir]       ;# Matching real clock latency
 
+set clk_port [get_ports $clk_port_name]
 set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_reg_outputs  [lsearch -inline -all -not -exact [all_outputs] [get_ports io_lsbs_*]]
+
+set_input_delay  [expr $clk_period * $clk_in_pct] -clock ${clk_name}_vir $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_o1_pct] -clock ${clk_name}_vir $non_reg_outputs
+set_output_delay [expr $clk_period * $clk_o2_pct] -clock ${clk_name}_vir [get_ports io_lsbs_*]
 
-set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+set_max_transition 300 [current_design]
+set_max_transition 100 -clock_path [all_clocks]

flow/designs/asap7/mock-array/constraints.sdc

@@ -3,7 +3,7 @@
 # current unit is configured as 2.16 which is on the routing grid for M5
 
 # table of Elements - (rows cols width height pitch_x pitch_y)
-export MOCK_ARRAY_TABLE         ?= 8 8 20 20 20 21
+export MOCK_ARRAY_TABLE         ?= 8 8 20 20 20 22
 
 # Element'd data width
 export MOCK_ARRAY_DATAWIDTH     ?= 64

flow/designs/asap7/mock-array/defaults.mk

@@ -28,5 +28,6 @@ add_pdn_connect -grid {top} -layers {M5 M6}
 # Element grid
 ####################################
 # The halo around the macro prevents pdn from blocking pin access
-define_pdn_grid -macro -cells Element -halo "3.0 3.0 3.0 3.0" -voltage_domains {CORE} -name ElementGrid
+define_pdn_grid -macro -cells Element -halo "0.25 0.25 0.25 0.25" -voltage_domains {CORE} -name ElementGrid
+
 add_pdn_connect -grid {ElementGrid} -layers {M5 M6}

flow/designs/asap7/mock-array/metadata-base-ok.json

@@ -4,7 +4,7 @@
         "compare": "<="
     },
     "constraints__clocks__count": {
-        "value": 1,
+        "value": 2,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
@@ -20,35 +20,31 @@
         "compare": "=="
     },
     "cts__timing__setup__ws": {
-        "value": 0.0,
+        "value": -199.73,
         "compare": ">="
     },
     "cts__timing__setup__ws__pre_repair": {
-        "value": 0.0,
+        "value": -227.1,
         "compare": ">="
     },
     "cts__timing__setup__ws__post_repair": {
-        "value": 0.0,
+        "value": -188.74,
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
         "value": 100,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 26044,
+        "value": 536,
         "compare": "<="
     },
-    "globalroute__timing__clock__slack": {
-        "value": 0.0,
-        "compare": ">="
-    },
     "globalroute__timing__setup__ws": {
         "value": 0.0,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 272158,
+        "value": 73815,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {