Merge pull request #3254 from The-OpenROAD-Project-staging/secure-mv-repair_tie-to-floorplan

Move repair_tie_fanout to floorplan.tcl

Author: maliberty

docs/user/FlowVariables.md

@@ -323,6 +323,8 @@ configuration file.
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [TAPCELL_TCL](#TAPCELL_TCL)
+- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
+- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## place variables
@@ -344,8 +346,6 @@ configuration file.
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
-- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
-- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [TIE_SEPARATION](#TIE_SEPARATION)
 
 ## cts variables

flow/designs/gf180/jpeg/rules-base.json

@@ -8,31 +8,31 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 2366631,
+        "value": 2362986,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 53829,
+        "value": 53818,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 4681,
+        "value": 4680,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 4681,
+        "value": 4680,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 2985307,
+        "value": 2973166,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -44,7 +44,7 @@
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
-        "value": 6,
+        "value": 10,
         "compare": "<="
     },
     "finish__timing__setup__ws": {

flow/scripts/floorplan.tcl

@@ -95,6 +95,10 @@ if { [env_var_exists_and_non_empty FOOTPRINT_TCL] } {
   log_cmd source $::env(FOOTPRINT_TCL)
 }
 
+# This needs to come before any call to remove_buffers.  You could have one
+# tie driving multiple buffers that drive multiple outputs.
+repair_tie_fanout_helper
+
 if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
   # remove buffers inserted by yosys/abc
   remove_buffers

flow/scripts/resize.tcl

@@ -16,26 +16,6 @@ if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } {
 
 repair_design_helper
 
-if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
-  set tie_separation $env(TIE_SEPARATION)
-} else {
-  set tie_separation 0
-}
-
-# Repair tie lo fanout
-puts "Repair tie lo fanout..."
-set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0]
-set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $tie_separation $tielo_pin
-
-# Repair tie hi fanout
-puts "Repair tie hi fanout..."
-set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0]
-set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $tie_separation $tiehi_pin
-
 # hold violations are not repaired until after CTS
 
 # post report

flow/scripts/util.tcl

@@ -13,6 +13,28 @@ proc log_cmd { cmd args } {
   return $result
 }
 
+proc repair_tie_fanout_helper {} {
+  if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
+    set tie_separation $env(TIE_SEPARATION)
+  } else {
+    set tie_separation 0
+  }
+
+  # Repair tie lo fanout
+  puts "Repair tie lo fanout..."
+  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
+  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
+  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $tie_separation $tielo_pin
+
+  # Repair tie hi fanout
+  puts "Repair tie hi fanout..."
+  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
+  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
+  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $tie_separation $tiehi_pin
+}
+
 proc fast_route { } {
   if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
     log_cmd source $::env(FASTROUTE_TCL)

flow/scripts/variables.yaml

@@ -215,13 +215,13 @@ TIEHI_CELL_AND_PORT:
     Netlist.
   stages:
     - synth
-    - place
+    - floorplan
 TIELO_CELL_AND_PORT:
   description: |
     Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.
   stages:
     - synth
-    - place
+    - floorplan
 TIE_SEPARATION:
   description: |
     Distance separating tie high/low instances from the load.