keep name consistency between flag/orfs variable and fix .yaml

Signed-off-by: Arthur Koucher <[email protected]>

Author: AcKoucher

flow/Makefile

@@ -211,7 +211,7 @@ export ENABLE_DPO ?= 1
 export DPO_MAX_DISPLACEMENT ?= 5 1
 
 # Settings for Sizing
-export HONOR_CELL_FOOTPRINT ?= 0
+export MATCH_CELL_FOOTPRINT ?= 0
 
 # Setup working directories
 export DESIGN_NICKNAME ?= $(DESIGN_NAME)

flow/scripts/util.tcl

@@ -27,7 +27,7 @@ proc repair_timing_helper { {hold_margin 1} } {
   append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0
   append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0
   append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0
-  append_env_var additional_args HONOR_CELL_FOOTPRINT -match_cell_footprint 0
+  append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   puts "repair_timing [join $additional_args " "]"
   repair_timing {*}$additional_args
 }
@@ -38,7 +38,7 @@ proc repair_design_helper {} {
   set additional_args ""
   append_env_var additional_args CAP_MARGIN -cap_margin 1
   append_env_var additional_args SLEW_MARGIN -slew_margin 1
-  append_env_var additional_args HONOR_CELL_FOOTPRINT -match_cell_footprint 0
+  append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   puts "repair_design [join $additional_args " "]"
 
   repair_design {*}$additional_args
@@ -55,7 +55,7 @@ proc recover_power {} {
   report_power
   set additional_args ""
   append_env_var additional_args RECOVER_POWER -recover_power 1
-  append_env_var additional_args HONOR_CELL_FOOTPRINT -match_cell_footprint 0
+  append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   repair_timing {*}$additional_args
   report_tns
   report_wns

flow/scripts/variables.yaml

@@ -622,10 +622,11 @@ GLOBAL_ROUTE_ARGS:
   stages:
     - grt
   default: -congestion_iterations 30 -congestion_report_iter_step 5 -verbose
-HONOR_CELL_FOOTPRINT:
+MATCH_CELL_FOOTPRINT:
   description: >
     Enforce sizing operations to only swap cells that have the same layout boundary.
   stages:
     - floorplan
     - place
     - cts
+    - route