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Merge commit 'refs/pull/1157/head' of https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts into HEAD
2 parents f580d3e + acd9292 commit e71bba9

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‎flow/Makefile‎

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# ==============================================================================
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# DESIGN_CONFIG=./designs/nangate45/aes/config.mk
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# DESIGN_CONFIG=./designs/nangate45/ariane133/config.mk
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# DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
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# DESIGN_CONFIG=./designs/nangate45/black_parrot/config.mk
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# DESIGN_CONFIG=./designs/nangate45/bp_be_top/config.mk
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# DESIGN_CONFIG=./designs/nangate45/bp_fe_top/config.mk
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# DESIGN_CONFIG=./designs/nangate45/bp_multi_top/config.mk
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# DESIGN_CONFIG=./designs/nangate45/bp_quad/config.mk
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# DESIGN_CONFIG=./designs/nangate45/dynamic_node/config.mk
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# DESIGN_CONFIG=./designs/nangate45/gcd/config.mk
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# DESIGN_CONFIG=./designs/nangate45/ibex/config.mk
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# DESIGN_CONFIG=./designs/nangate45/jpeg/config.mk
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# DESIGN_CONFIG=./designs/nangate45/mempool_group/config.mk
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# DESIGN_CONFIG=./designs/nangate45/swerv/config.mk
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# DESIGN_CONFIG=./designs/nangate45/swerv_wrapper/config.mk
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# DESIGN_CONFIG=./designs/nangate45/tiny-tests/config.mk
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# DESIGN_CONFIG=./designs/nangate45/tinyRocket/config.mk
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# DESIGN_CONFIG=./designs/tsmc65lp/aes/config.mk
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# DESIGN_CONFIG=./designs/gf12/ariane/config.mk
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# DESIGN_CONFIG=./designs/gf12/ca53/config.mk
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# DESIGN_CONFIG=./designs/gf12/coyote/config.mk
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# DESIGN_CONFIG=./designs/gf12/dynamic_node/config.mk
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# DESIGN_CONFIG=./designs/gf12/gcd/config.mk
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# DESIGN_CONFIG=./designs/gf12/ibex/config.mk
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# DESIGN_CONFIG=./designs/gf12/jpeg/config.mk
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# DESIGN_CONFIG=./designs/gf12/swerv/config.mk
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# DESIGN_CONFIG=./designs/gf12/swerv_wrapper/config.mk
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# DESIGN_CONFIG=./designs/gf12/tinyRocket/config.mk
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# DESIGN_CONFIG=./designs/gf12/bsg_padring/config.mk
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# DESIGN_CONFIG=./designs/gf12/bsg_loopback/config.mk
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# DESIGN_CONFIG=./designs/gf12/bp_single/config.mk
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# DESIGN_CONFIG=./designs/gf12/ariane133/config.mk
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# DESIGN_CONFIG=./designs/gf12/bp_dual/config.mk
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# DESIGN_CONFIG=./designs/gf12/bp_quad/config.mk
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# DESIGN_CONFIG=./designs/gf12/bp_single/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/aes/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/chameleon/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/chameleon_hier/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/coyote_tc/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/aes/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/jpeg/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/coyote_tc/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/chameleon/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/microwatt/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/sky130hd/chameleon_hier/config.mk
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# DESIGN_CONFIG=./designs/sky130hs/aes/config.mk
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# DESIGN_CONFIG=./designs/sky130hs/gcd/config.mk
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# DESIGN_CONFIG=./designs/sky130hs/ibex/config.mk
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# DESIGN_CONFIG=./designs/sky130hs/aes/config.mk
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# DESIGN_CONFIG=./designs/sky130hs/jpeg/config.mk
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# DESIGN_CONFIG=./designs/sky130hs/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/asap7/aes/config.mk
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# DESIGN_CONFIG=./designs/asap7/ethmac/config.mk
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# DESIGN_CONFIG=./designs/asap7/gcd/config.mk
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# DESIGN_CONFIG=./designs/asap7/ibex/config.mk
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# DESIGN_CONFIG=./designs/asap7/aes/config.mk
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# DESIGN_CONFIG=./designs/asap7/jpeg/config.mk
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# DESIGN_CONFIG=./designs/asap7/ethmac/config.mk
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# DESIGN_CONFIG=./designs/asap7/uart/config.mk
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# DESIGN_CONFIG=./designs/asap7/sha3/config.mk
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# DESIGN_CONFIG=./designs/asap7/megaboom/config.mk
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# DESIGN_CONFIG=./designs/asap7/mock-array-big/config.mk
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# DESIGN_CONFIG=./designs/asap7/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/asap7/sha3/config.mk
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# DESIGN_CONFIG=./designs/asap7/swerv_wrapper/config.mk
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# DESIGN_CONFIG=./designs/asap7/uart-blocks/config.mk
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# DESIGN_CONFIG=./designs/asap7/uart/config.mk
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# DESIGN_CONFIG=./designs/intel16/aes/config.mk
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# DESIGN_CONFIG=./designs/intel16/gcd/config.mk
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# DESIGN_CONFIG=./designs/intel22/gcd/config.mk
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# DESIGN_CONFIG=./designs/intel22/aes/config.mk
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# DESIGN_CONFIG=./designs/intel22/gcd/config.mk
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# DESIGN_CONFIG=./designs/intel22/ibex/config.mk
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# DESIGN_CONFIG=./designs/intel22/jpeg/config.mk
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# DESIGN_CONFIG=./designs/gf180/aes/config.mk
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# DESIGN_CONFIG=./designs/gf180/ibex/config.mk
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# DESIGN_CONFIG=./designs/gf180/jpeg/config.mk
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# DESIGN_CONFIG=./designs/gf180/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/gf180/sha3/config.mk
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# DESIGN_CONFIG=./designs/gf180/uart-blocks/config.mk
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#
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# Default design
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DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk

‎flow/designs/asap7/mock-array/Element/config.mk‎

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@@ -36,3 +36,8 @@ export PDN_TCL = designs/asap7/mock-array/Element/pdn.tcl
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# At time of adding this option, only 3 iterations were needed for 0
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# violations.
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export DETAILED_ROUTE_ARGS=-bottom_routing_layer M2 -top_routing_layer M5 -save_guide_updates -verbose 1 -droute_end_iter 10
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# since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
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# same information to other stages in the flow.
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export MIN_ROUTING_LAYER = M2
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export MAX_ROUTING_LAYER = M5

‎flow/designs/asap7/mock-array/README.md‎

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```
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make
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```
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Element/constraint.sdc
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----------------------
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A relatively simple constraint.sdc is adequate for the Element as
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timing is exported when the Element macro is made and checked at the
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mock-array-big level.
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Note that a failure on timing at the Element level is
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not a problem, as long as timing is met at the mock-array-big level.
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The purpose of the constraint.sdc file at the Element level is to
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be able to iterate on the Element during development and work on,
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for instance, maximum operating frequency changes in the Verilog,
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but also to give the tools some guidance on how to optimize the
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macro.
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Optimizing Element/constraint.sdc
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---------------------------------
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Before considering the various strategies to articulate an Element/constraint.sdc
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file below, note that no tests have been run to verify that these
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different constraint.sdc changes below have any effects on the quality
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of results at the mock-array-big level. If there are no substantial
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differences in quality of results and timing is met, then the differences
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between the strategies below are inconsequential.
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A single macro is made for all the elements in the array, though strictly
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speaking each macro is unique in that the timing constraints of each element
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in the array is different.
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To illustrate, consider the `assign io_lsbOuts_0 = io_lsbIns_1;` statement in Element.v.
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Here a signal is routed from left to right, through the Element without the signal
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being registered.
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Clearly, the maximum input delay for `io_lsbIns_1` is
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smaller for the leftmost than for the rightmost Element.
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Taking a step back, it is also worth considering what level of detail is
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appropriate for the Element's constraint.sdc file.
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In the beginning of a project, during exploration, the .sdc file does not
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need to be particularly detailed. In fact, details can be counterproductive,
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as they tend to be inaccurate and cause the tools to spend time solving potential non-issues.
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Consider minimum input delay, which relates to hold times. If the main concern
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of architectural exploration is to ensure that the design can operate on a
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sufficiently high frequency, then specifying minimum input delays during
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exploration is premature. Minimum input delay is a constraint that belongs at
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the end the development cycle when the design is well established and won't change
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and the concern is to lock down the macro for its specific operating frequency.
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Choosing a strategy for Element/constraint.sdc combinational paths
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------------------------------------------------------------------
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It isn't possible to articulate a single .sdc file that exactly captures the
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constraints of an Element as each element is used in unique circumstances.
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Instead, a choice has to made and each choice has its pros and cons.
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It is relatively easy to set up a maximum input/output delay for paths
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that start or end in a register, so this case is not discussed here.
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It is the combinational(unregistered) in -> out
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paths that are tricky to create constraints for.
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- Strategy used as of writing: mark non-registered/combinational paths through
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the Element as false paths. This will not steer the tools to optimize the
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through element path, such as discussed above and there's no timing information
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available at the Element level for these combinational paths.
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However, at the `MockArray` level when the Elements are used, timing will
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be checked, because the .lib file generated for the Element contains timing
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information, even for false paths.
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- Use `set_max_delay` for combinational paths. This will make the tool try
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to optimize the combinational path and there will be timing information available.
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However, path segmentation could occur with OpenSTA. Refer [here](https://docs.xilinx.com/r/2020.2-English/ug906-vivado-design-analysis/TIMING-13-Timing-Paths-Ignored-Due-to-Path-Segmentation).
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- Overconstrain: set up a maximum input/output path for the element and ignore
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timing violations at the Element level for combinational paths.
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The timing violations for the combinational paths are not real violations,
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because the maximum input and output paths can not occur at the same time
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in the array. The leftmost Element has the shortest maximum input path and
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and the rightmost the longest maximum input path for
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`assign io_lsbOuts_0 = io_lsbIns_1;`. The OpenROAD tool could put too much
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emphasis on optimising the combinational path in this case, which could
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lead to less than optimal results and/or inflated run times.

‎flow/designs/asap7/mock-array/config.mk‎

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# At time of adding this option, only 12 iterations were needed for 0
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# violations.
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export DETAILED_ROUTE_ARGS=-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 15
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# since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
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# same information to other stages in the flow.
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export MIN_ROUTING_LAYER = M2
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export MAX_ROUTING_LAYER = M7

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