Merge branch 'master' into secure-sta_fix

Signed-off-by: Eder Monteiro <[email protected]>

Author: eder-matheus

docs/user/FlowVariables.md

@@ -238,6 +238,7 @@ configuration file.
 - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT)
 - [PDN_TCL](#PDN_TCL)
 - [PLACE_DENSITY](#PLACE_DENSITY)
+- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [PLACE_SITE](#PLACE_SITE)
 - [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
@@ -282,6 +283,7 @@ configuration file.
 - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER)
 - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
 - [PLACE_DENSITY](#PLACE_DENSITY)
+- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
@@ -387,7 +389,6 @@ configuration file.
 - [KLAYOUT_TECH_FILE](#KLAYOUT_TECH_FILE)
 - [LIB_FILES](#LIB_FILES)
 - [MACRO_EXTENSION](#MACRO_EXTENSION)
-- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
 - [PLATFORM](#PLATFORM)
 - [PRESERVE_CELLS](#PRESERVE_CELLS)
 - [PROCESS](#PROCESS)

flow/BUILD.bazel

@@ -9,7 +9,7 @@ module(
 bazel_dep(name = "bazel-orfs")
 git_override(
     module_name = "bazel-orfs",
-    commit = "d30e1987275cb54163a4dfde421392c31d0a7148",
+    commit = "f11fbdb35eeae7f8d5e08a58fb7d040f11cb9f04",
     remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
 )
 

flow/MODULE.bazel

@@ -48,7 +48,7 @@ orfs_sweep(
         for value in SWEEPS[SWEEP]
     },
     top = "ethmac",
-    verilog_files = ["//:ethmac_lvt_src"],
+    verilog_files = ["//designs/src/ethmac_lvt:verilog"],
 )
 
 plot_congestion(

flow/MODULE.bazel.lock

@@ -0,0 +1,47 @@
+load("@bazel-orfs//:sweep.bzl", "orfs_sweep")
+load("//util:plot_congestion.bzl", "plot_congestion")
+
+# Format densities, rounding to 2 decimal places.
+SWEEPS = {
+    "PLACE_DENSITY": [str(0.35 + x * 0.01 + 0.005)[:4] for x in range(65)],
+    "CORE_UTILIZATION": [str(40 + x * 5) for x in range(4)],
+}
+
+SWEEP = "PLACE_DENSITY"
+
+orfs_sweep(
+    name = "gcd",
+    arguments = {
+        # Faster builds
+        "SKIP_INCREMENTAL_REPAIR": "1",
+        "GPL_TIMING_DRIVEN": "0",
+        "SKIP_LAST_GASP": "1",
+        # Various
+        "DIE_AREA": "0 0 16.2 16.2",
+        "CORE_AREA": "1.08 1.08 15.12 15.12",
+        "PLACE_DENSITY": "0.35",
+    },
+    other_variants = {"base": {}},
+    sources = {
+        "SDC_FILE": [":constraint.sdc"],
+    },
+    sweep = {
+        value: {
+            "arguments": {
+                SWEEP: value,
+            },
+            "previous_stage": {
+                "floorplan": "gcd_synth",
+            },
+        }
+        for value in SWEEPS[SWEEP]
+    },
+    verilog_files = ["//designs/src/gcd:verilog"],
+)
+
+plot_congestion(
+    name = "plot",
+    srcs = [":gcd_{value}_grt".format(value = value) for value in SWEEPS[SWEEP]],
+    argument = SWEEP,
+    values = SWEEPS[SWEEP],
+)

flow/designs/asap7/ethmac_lvt/BUILD.bazel

@@ -7,6 +7,8 @@ export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constr
 
 export DIE_AREA               = 0 0 16.2 16.2
 export CORE_AREA              = 1.08 1.08 15.12 15.12
+# The goal of this design is to have a smoketest that builds quickly,
+# that said, this design will go through grt with a 0.99 placement density.
 export PLACE_DENSITY          = 0.35
 
 # a smoketest for this option, there are a

flow/designs/asap7/gcd/BUILD.bazel

@@ -0,0 +1,57 @@
+load("@bazel-orfs//:sweep.bzl", "orfs_sweep")
+load("//util:plot_congestion.bzl", "plot_congestion")
+
+# Format densities, rounding to 2 decimal places.
+SWEEPS = {
+    "PLACE_DENSITY_LB_ADDON": [str(0.20 + x * 0.01 + 0.005)[:4] for x in range(10)],
+    "CORE_UTILIZATION": [str(40 + x * 5) for x in range(4)],
+}
+
+SWEEP = "PLACE_DENSITY_LB_ADDON"
+
+orfs_sweep(
+    name = "swerv_wrapper",
+    arguments = {
+        "LIB_MODEL": "CCS",
+        "SYNTH_HIERARCHICAL": "1",
+        "RTLMP_MAX_INST": "30000",
+        "RTLMP_MIN_INST": "5000",
+        "RTLMP_MAX_MACRO": "30",
+        "RTLMP_MIN_MACRO": "4",
+        "DIE_AREA": "0 0 550 600",
+        "CORE_AREA": "5 5 545 595",
+        "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*",
+        "PLACE_DENSITY_LB_ADDON": "0.20",
+        "TNS_END_PERCENT": "100",
+        "PWR_NETS_VOLTAGEsS": "",
+        "GND_NETS_VOLTAGES": "",
+    },
+    other_variants = {"base": {}},
+    sources = {
+        "ADDITIONAL_LEFS": glob(include = ["lef/*.lef"]),
+        "ADDITIONAL_LIBS": glob(include = ["lib/*.lib"]),
+        "SDC_FILE": [":constraint.sdc"],
+    },
+    sweep = {
+        value: {
+            "arguments": {
+                SWEEP: value,
+            },
+            "previous_stage": {
+                "floorplan": "swerv_wrapper_synth",
+            },
+        }
+        for value in SWEEPS[SWEEP]
+    },
+    verilog_files = [
+        "macros.v",
+        "//designs/src/swerv:verilog",
+    ],
+)
+
+plot_congestion(
+    name = "plot",
+    srcs = [":swerv_wrapper_{value}_grt".format(value = value) for value in SWEEPS[SWEEP]],
+    argument = SWEEP,
+    values = SWEEPS[SWEEP],
+)

flow/designs/asap7/gcd/config.mk

@@ -0,0 +1,5 @@
+filegroup(
+    name = "verilog",
+    srcs = glob(include = ["*.v"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/asap7/swerv_wrapper/BUILD.bazel

@@ -0,0 +1,5 @@
+filegroup(
+    name = "verilog",
+    srcs = glob(include = ["*.v"]),
+    visibility = ["//visibility:public"],
+)