Merge branch 'master' into gf12-bp-quad-dual

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

.github/workflows/github-actions-yaml-test.yml

@@ -11,6 +11,12 @@ jobs:
     steps:
     - name: Checkout repository
       uses: actions/checkout@v4
+      with:
+        fetch-depth: 1
+        sparse-checkout: |
+          flow/scripts/generate-variables-docs.py
+          docs/user/FlowVariables.md
+          yamlfix.toml
     - name: Run generate-variables-docs.py
       run: |
         python3 flow/scripts/generate-variables-docs.py
@@ -19,5 +25,8 @@ jobs:
         git diff --exit-code docs/user/FlowVariables.md
     - name: Run yamlfix check
       run: |
-        pip install yamlfix==1.17.0
-        yamlfix -c yamlfix.toml flow/scripts/variables.yaml --check
+        pip install --quiet yamlfix==1.17.0
+        yamlfix --version
+        set -x
+        yamlfix -c yamlfix.toml flow/scripts/variables.yaml
+        git diff flow/scripts/variables.yaml

docs/user/FlowVariables.md

@@ -122,7 +122,6 @@ configuration file.
 | <a name="MAKE_TRACKS"></a>MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | |
 | <a name="MATCH_CELL_FOOTPRINT"></a>MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| |
 | <a name="MAX_ROUTING_LAYER"></a>MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | |
-| <a name="MAX_UNGROUP_SIZE"></a>MAX_UNGROUP_SIZE| For hierarchical synthesis, we ungroup modules of larger area than given by this variable. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| | |
 | <a name="MIN_BUF_CELL_AND_PORTS"></a>MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | |
 | <a name="MIN_ROUTING_LAYER"></a>MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | |
 | <a name="PDN_TCL"></a>PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | |
@@ -183,7 +182,9 @@ configuration file.
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
+| <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| | |
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
+| <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | |
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | |
@@ -204,15 +205,16 @@ configuration file.
 - [ADDER_MAP_FILE](#ADDER_MAP_FILE)
 - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE)
 - [LATCH_MAP_FILE](#LATCH_MAP_FILE)
-- [MAX_UNGROUP_SIZE](#MAX_UNGROUP_SIZE)
 - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
+- [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE)
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
+- [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [VERILOG_FILES](#VERILOG_FILES)

flow/Makefile

@@ -160,7 +160,7 @@ include $(PLATFORM_DIR)/config.mk
 $(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
 
 # If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here
-export MAX_UNGROUP_SIZE ?= 0
+export SYNTH_MINIMUM_KEEP_SIZE ?= 0
 
 # Not normally adjusted by user
 export SYNTH_OPERATIONS_ARGS ?= -extra-map $(FLOW_HOME)/platforms/common/lcu_kogge_stone.v
@@ -1026,6 +1026,11 @@ run:
 	@mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
 	($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) 2>&1 | tee $(abspath $(LOG_DIR)/$(RUN_LOG_NAME_STEM).log))
 
+export RUN_YOSYS_ARGS ?= -c $(SCRIPTS_DIR)/yosys_keep.tcl
+.phony: run-yosys
+run-yosys:
+	$(YOSYS_EXE) $(RUN_YOSYS_ARGS)
+
 # Utilities
 #-------------------------------------------------------------------------------
 include $(UTILS_DIR)/utils.mk

flow/designs/asap7/aes-block/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 72180,
+        "value": 71923,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -89.24,
+        "value": -86.6,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 7362,
+        "value": 7354,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
         "value": 478,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 388,
+        "value": 326,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -21.75,
+        "value": -21.47,
         "compare": ">="
     }
 }

flow/designs/asap7/aes-mbff/rules-base.json

@@ -48,11 +48,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -78.86,
+        "value": -68.71,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 2360,
+        "value": 2359,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -23.22,
+        "value": -21.4,
         "compare": ">="
     }
 }

flow/designs/asap7/aes/README.md

@@ -3,7 +3,7 @@
 For large designs, it can be useful to split synthesis for the
 major blocks and combine the synthesized result.
 
-SYNTH_HIERARCHICAL=1 and MAX_UNGROUP_SIZE can be used to adjust which
+SYNTH_HIERARCHICAL=1 and SYNTH_MINIMUM_KEEP_SIZE can be used to adjust which
 modules are flattened and which are kept.
 
 A module that is not flattened, can be built separately without any

flow/designs/asap7/aes/rules-base.json

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -66.42,
+        "value": -61.05,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -20.87,
+        "value": -19.6,
         "compare": ">="
     }
 }

flow/designs/asap7/gcd-ccs/rules-base.json

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -80.19,
+        "value": -79.79,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -34.82,
+        "value": -34.7,
         "compare": ">="
     }
 }

flow/designs/asap7/gcd/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1454,
+        "value": 1451,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {

flow/designs/asap7/ibex/rules-base.json

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -127.02,
+        "value": -108.44,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -17.16,
+        "value": -15.17,
         "compare": ">="
     }
 }