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lines changed Original file line number Diff line number Diff line change @@ -7,6 +7,5 @@ export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
77# Adders degrade GCD
88export ADDER_MAP_FILE :=
99
10- # These values must be multiples of placement site
11- export DIE_AREA = 0 0 279.96 280.128
12- export CORE_AREA = 9.996 10.08 269.964 270.048
10+ export CORE_UTILIZATION = 40
11+ export PLACE_DENISTY_LB_ADDON = 0.1
Original file line number Diff line number Diff line change @@ -45,10 +45,5 @@ export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
4545# Adders degrade ibex setup repair
4646export ADDER_MAP_FILE :=
4747
48- export CORE_UTILIZATION = 40
49- export CORE_ASPECT_RATIO = 1
50- export CORE_MARGIN = 2
51-
48+ export CORE_UTILIZATION = 45
5249export PLACE_DENSITY_LB_ADDON = 0.2
53-
54- export FASTROUTE_TCL = $(PLATFORM_DIR ) /fastroute_base.tcl
Original file line number Diff line number Diff line change @@ -6,8 +6,5 @@ export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
66export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME ) /include
77export SDC_FILE = ./designs/$(PLATFORM ) /$(DESIGN_NICKNAME ) /constraint.sdc
88
9- export CORE_UTILIZATION = 50
10- export CORE_ASPECT_RATIO = 1
11- export CORE_MARGIN = 2
12-
13- export PLACE_DENSITY_LB_ADDON = 0.25
9+ export CORE_UTILIZATION = 55
10+ export PLACE_DENSITY_LB_ADDON = 0.20
Original file line number Diff line number Diff line change @@ -5,8 +5,5 @@ export PLATFORM = sky130hd
55export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME ) /* .v) )
66export SDC_FILE = ./designs/$(PLATFORM ) /$(DESIGN_NICKNAME ) /constraint.sdc
77
8- export CORE_UTILIZATION = 40
9- export CORE_ASPECT_RATIO = 1
10- export CORE_MARGIN = 2
11- #
8+ export CORE_UTILIZATION = 45
129export PLACE_DENSITY_LB_ADDON = 0.2
Original file line number Diff line number Diff line change @@ -8,6 +8,5 @@ export ABC_AREA = 1
88# Adders degrade GCD
99export ADDER_MAP_FILE :=
1010
11- # These values must be multiples of placement site
12- export DIE_AREA = 0 0 279.96 280.128
13- export CORE_AREA = 9.996 10.08 269.964 270.048
11+ export CORE_UTILIZATION = 40
12+ export PLACE_DENSITY_LB_ADDON = 0.1
Original file line number Diff line number Diff line change @@ -41,11 +41,5 @@ export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \
4141 ./designs/src/$(DESIGN_NICKNAME ) /prim_xilinx_clock_gating.v
4242export SDC_FILE = ./designs/$(PLATFORM ) /$(DESIGN_NICKNAME ) /constraint.sdc
4343
44- export CORE_UTILIZATION = 40
45- export CORE_ASPECT_RATIO = 1
46- export CORE_MARGIN = 2
47-
44+ export CORE_UTILIZATION = 45
4845export PLACE_DENSITY_LB_ADDON = 0.2
49-
50- export FASTROUTE_TCL = $(PLATFORM_DIR ) /fastroute_base.tcl
51-
Original file line number Diff line number Diff line change @@ -7,10 +7,7 @@ export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
77export ABC_CLOCK_PERIOD_IN_PS = 4000
88
99
10- export CORE_UTILIZATION = 40
11- export CORE_ASPECT_RATIO = 1
12- export CORE_MARGIN = 2
13-
10+ export CORE_UTILIZATION = 45
1411export PLACE_DENSITY_LB_ADDON = 0.2
1512# many east pins cause global routing congestion
1613export PLACE_PINS_ARGS =-min_distance 6 -min_distance_in_tracks
Original file line number Diff line number Diff line change @@ -30,7 +30,7 @@ if {[info exists ::env(FLOORPLAN_DEF)]} {
3030 if {[info exists ::env(CORE_ASPECT_RATIO)] && $::env(CORE_ASPECT_RATIO) != " " } {
3131 set aspect_ratio $::env(CORE_ASPECT_RATIO)
3232 }
33- set core_margin " 1.0"
33+ set core_margin 1.0
3434 if {[info exists ::env(CORE_MARGIN)] && $::env(CORE_MARGIN) != " " } {
3535 set core_margin $::env(CORE_MARGIN)
3636 }
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