@@ -384,16 +384,33 @@ HOLD_SLACK_MARGIN:
384384 This option allows you to overfix or underfix(negative value, terminate
385385 retiming before 0 or positive slack).
386386
387- Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan .
387+ floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0(default hold slack margin).
388388
389389 This avoids overrepair in floorplan for hold by default, but allows skipping
390390 hold repair using a negative HOLD_SLACK_MARGIN.
391391
392392 Exiting timing repair early is useful in exploration where
393-
394393 the .sdc has a fixed clock period at designs target clock period and where
395394 HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running
396395 times) when exploring different parameter settings.
396+
397+ When an ideal clock is used, that is before CTS,
398+ a clock insertion delay of 0 is used in timing paths. This creates
399+ a mismatch between macros that have a .lib file from after CTS, when
400+ the clock is propagated. To mitigate this, OpenSTA will use subtract
401+ the clock insertion delay of macros when calculating timing.
402+ This works with macros built with OpenROAD that have min_clock_tree_path
403+ and max_clock_tree_path set. This is less accurate than if OpenROAD had
404+ created a placeholder clock tree for timing estimation purposes
405+ prior to CTS.
406+
407+ There will inevitably be inaccuracies in the timing calculation prior
408+ to CTS. Use a slack margin that is low enough, even negative, to
409+ avoid overrepair.
410+
411+ Overrepair can lead to excessive runtimes in repair or too much buffering
412+ being added, which can present itself as congestion of hold cells or
413+ buffer cells.
397414 stages :
398415 - cts
399416 - floorplan
@@ -404,6 +421,8 @@ SETUP_SLACK_MARGIN:
404421 Specifies a time margin for the slack when fixing setup violations.
405422 This option allows you to overfix or underfix(negative value, terminate
406423 retiming before 0 or positive slack).
424+
425+ See HOLD_SLACK_MARGIN for more details.
407426 stages :
408427 - cts
409428 - floorplan
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