Replace SYNTH_USE_SLANG with SYNTH_HDL_FRONTEND

povik · povik · commit ed7902e1e053 · 2025-05-02T21:08:22.000+02:00
Signed-off-by: Martin Povišer &lt;povik@cutebit.org&gt;
diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
@@ -182,12 +182,12 @@ configuration file.
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| |
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
+| <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
 | <a name="SYNTH_KEEP_MODULES"></a>SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
 | <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| |
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
-| <a name="SYNTH_USE_SLANG"></a>SYNTH_USE_SLANG| Use yosys-slang for read-in of SystemVerilog design.| 0| |
 | <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | |
@@ -215,12 +215,12 @@ configuration file.
 - [SDC_GUT](#SDC_GUT)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
+- [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
 - [SYNTH_KEEP_MODULES](#SYNTH_KEEP_MODULES)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
 - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE)
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
-- [SYNTH_USE_SLANG](#SYNTH_USE_SLANG)
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk
@@ -193,4 +193,4 @@ export PLACE_DENSITY          = 0.50
 export SKIP_LAST_GASP ?= 1
 
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
diff --git a/flow/designs/asap7/ibex/config.mk b/flow/designs/asap7/ibex/config.mk
@@ -9,7 +9,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 # if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock
 # resulting in positive slack
diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk
@@ -8,7 +8,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/gf180/ibex/config.mk b/flow/designs/gf180/ibex/config.mk
@@ -8,7 +8,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/ihp-sg13g2/ibex/config.mk b/flow/designs/ihp-sg13g2/ibex/config.mk
@@ -8,7 +8,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/intel16/ibex/config.mk b/flow/designs/intel16/ibex/config.mk
@@ -10,7 +10,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_DIR)/constraint.sdc
 
diff --git a/flow/designs/nangate45/ibex/config.mk b/flow/designs/nangate45/ibex/config.mk
@@ -8,7 +8,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/nangate45/mempool_group/config.mk b/flow/designs/nangate45/mempool_group/config.mk
@@ -77,4 +77,4 @@ export CORE_AREA   = 10 12 1090 1090
 
 export MACRO_PLACE_HALO = 10 10
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk
@@ -8,7 +8,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk
@@ -8,7 +8,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
 export VERILOG_INCLUDE_DIRS = \
     $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl
@@ -43,21 +43,23 @@ proc read_design_sources {} {
     set vIdirsArgs [join $vIdirsArgs]
   }
 
-  if {[env_var_equals SYNTH_USE_SLANG 1]} {
+  if {[env_var_equals SYNTH_HDL_FRONTEND slang]} {
     # slang requires all files at once
     plugin -i slang
     yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \
       --ignore-assertions --top $::env(DESIGN_NAME) \
       {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env(VERILOG_DEFINES)
     # Workaround for yosys-slang#119
     setattr -unset init
-  } else {
+  } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} {
     verilog_defaults -push
     verilog_defaults -add {*}$::env(VERILOG_DEFINES)
     foreach file $::env(VERILOG_FILES) {
       read_verilog -defer -sv {*}$vIdirsArgs $file
     }
     verilog_defaults -pop
+  } else {
+    error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)" 
   }
 
   # Read platform specific mapfile for OPENROAD_CLKGATE cells
diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml
@@ -169,10 +169,11 @@ SYNTH_MEMORY_MAX_BITS:
   default: 4096
   stages:
     - synth
-SYNTH_USE_SLANG:
+SYNTH_HDL_FRONTEND:
   description: >
-    Use yosys-slang for read-in of SystemVerilog design.
-  default: 0
+    Select an alternative language frontend to ingest the design. Available option
+    is "slang". If the variable is empty, design is read with the Yosys read_verilog
+    command.
   stages:
     - synth
 SYNTH_BLACKBOXES:

Original file line number	Diff line number	Diff line change
`@@ -193,4 +193,4 @@ export PLACE_DENSITY = 0.50`
`193`	`193`	`export SKIP_LAST_GASP ?= 1`
`194`	`194`
`195`	`195`
`196`		`-export SYNTH_USE_SLANG = 1`
	`196`	`+export SYNTH_HDL_FRONTEND = slang`
Original file line number	Diff line number	Diff line change
`@@ -77,4 +77,4 @@ export CORE_AREA = 10 12 1090 1090`
`77`	`77`
`78`	`78`	`export MACRO_PLACE_HALO = 10 10`
`79`	`79`
`80`		`-export SYNTH_USE_SLANG = 1`
	`80`	`+export SYNTH_HDL_FRONTEND = slang`