Merge pull request #3246 from The-OpenROAD-Project-staging/rm-resynth

Remove RESYNTH_TIMING_RECOVER & RESYNTH_AREA_RECOVER

Author: maliberty

flow/scripts/floorplan.tcl

@@ -110,84 +110,11 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
   repair_timing_helper 0
 }
 
-##### Restructure for timing #########
-if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
-  repair_design_helper
-  repair_timing_helper
-  # pre restructure area/timing report (ideal clocks)
-  puts "Post synth-opt area"
-  report_design_area
-  report_worst_slack -min -digits 3
-  puts "Post synth-opt wns"
-  report_worst_slack -max -digits 3
-  puts "Post synth-opt tns"
-  report_tns -digits 3
-
-  write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v
-
-  restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \
-              -work_dir $::env(RESULTS_DIR)
-
-  write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v
-
-  # post restructure area/timing report (ideal clocks)
-  remove_buffers
-  repair_design_helper
-  repair_timing_helper
-
-  puts "Post restructure-opt wns"
-  report_worst_slack -max -digits 3
-  puts "Post restructure-opt tns"
-  report_tns -digits 3
-
-  # remove buffers inserted by optimization
-  remove_buffers
-}
-
-
 puts "Default units for flow"
 report_units
 report_units_metric
 report_metrics 2 "floorplan final" false false
 
-if { [env_var_equals RESYNTH_AREA_RECOVER 1] } {
-
-  utl::push_metrics_stage "floorplan__{}__pre_restruct"
-  set num_instances [llength [get_cells -hier *]]
-  puts "number instances before restructure is $num_instances"
-  puts "Design Area before restructure"
-  report_design_area
-  report_design_area_metrics
-  utl::pop_metrics_stage
-
-  write_verilog $::env(RESULTS_DIR)/2_pre_abc.v
-
-  set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0]
-  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-  set tielo_port $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1]
-
-  set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0]
-  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-  set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1]
-
-  restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \
-        -tiehi_port $tiehi_port \
-        -tielo_port $tielo_port \
-        -work_dir $::env(RESULTS_DIR)
-
-  # remove buffers inserted by abc
-  remove_buffers
-
-  write_verilog $::env(RESULTS_DIR)/2_post_abc.v
-  utl::push_metrics_stage "floorplan__{}__post_restruct"
-  set num_instances [llength [get_cells -hier *]]
-  puts "number instances after restructure is $num_instances"
-  puts "Design Area after restructure"
-  report_design_area
-  report_design_area_metrics
-  utl::pop_metrics_stage
-}
-
 if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } {
   log_cmd source $::env(POST_FLOORPLAN_TCL)
 }

flow/scripts/variables.yaml

@@ -708,18 +708,6 @@ DIE_AREA:
   stages:
     - floorplan
   tunable: 1
-RESYNTH_AREA_RECOVER:
-  description: |
-    Enable re-synthesis for area reclaim.
-  stages:
-    - floorplan
-  default: 0
-RESYNTH_TIMING_RECOVER:
-  description: |
-    Enable re-synthesis for timing optimization.
-  stages:
-    - floorplan
-  default: 0
 MACRO_ROWS_HALO_X:
   description: >
     Horizontal distance between the edge of the macro and the beginning of the