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flow: designs: ihp-sg13g2: Update I2C GPIO Expander
Move the I2cDeviceCtrl into a macro to have one chip design with an embedded macro generated by OR. Signed-off-by: Daniel Schultz <[email protected]>
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export DESIGN_NAME = I2cDeviceCtrl
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export TOP_DESIGN_NICKNAME = i2c-gpio-expander
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export DESIGN_NICKNAME = ${TOP_DESIGN_NICKNAME}_${DESIGN_NAME}
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export PLATFORM = ihp-sg13g2
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export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/${TOP_DESIGN_NICKNAME}/I2cGpioExpander.v \
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/constraint.sdc
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export DIE_AREA = 0.0 0.0 147.84 147.42
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export CORE_AREA = 18.72 18.9 128.64 128.52
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export MAX_ROUTING_LAYER = TopMetal2
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export TNS_END_PERCENT = 100
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export PLACE_DENSITY = 0.75
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export CORNERS = slow typ fast
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export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/pdn.tcl
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current_design I2cDeviceCtrl/I2cDeviceCtrl
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set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA
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set_max_fanout 8 [current_design]
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set_max_capacitance 0.5 [current_design]
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set_max_transition 3 [current_design]
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set_max_area 0
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create_clock [get_ports clock] -name clock -period 20.0 -waveform {0 10.0}
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set_ideal_network [get_ports clock]
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set_clock_uncertainty 0.15 [get_clocks clock]
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set_clock_transition 0.25 [get_clocks clock]
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set input_delay_value_clock 4.0
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set output_delay_value_clock 4.0
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set clk_indx_clock [lsearch [all_inputs] [get_port clock]]
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set all_inputs_wo_clk_rst_clock [lreplace [all_inputs] $clk_indx_clock $clk_indx_clock ""]
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set_input_delay $input_delay_value_clock -clock [get_clocks clock] $all_inputs_wo_clk_rst_clock
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set_output_delay $output_delay_value_clock -clock [get_clocks clock] [all_outputs]
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set_load -pin_load 5 [all_inputs]
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set_load -pin_load 5 [all_outputs]
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set_timing_derate -early 0.95
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set_timing_derate -late 1.05
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# standard cells
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add_global_connection -net {VDD} -pin_pattern {^VDD$} -power
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add_global_connection -net {VDD} -pin_pattern {^VDDPE$}
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add_global_connection -net {VDD} -pin_pattern {^VDDCE$}
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add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground
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add_global_connection -net {VSS} -pin_pattern {^VSSE$}
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# macros
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
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# padframe core power pins
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add_global_connection -net {VDD} -pin_pattern {^vdd$} -power
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add_global_connection -net {VSS} -pin_pattern {^vss$} -ground
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# padframe io power pins
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add_global_connection -net {IOVDD} -pin_pattern {^iovdd$} -power
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add_global_connection -net {IOVSS} -pin_pattern {^iovss$} -ground
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global_connect
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# core voltage domain
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set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
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# stdcell grid
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define_pdn_grid -name {grid} -voltage_domains {CORE}
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add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring
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add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads
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add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring
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add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} -extend_to_core_ring
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add_pdn_connect -grid {grid} -layers {Metal1 Metal3}
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add_pdn_connect -grid {grid} -layers {Metal3 Metal4}

flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk

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export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz
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export DIE_AREA = 0.0 0.0 1050.0 1050.0
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export CORE_AREA = 425.28 427.16 631.2 630.24
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export CORE_AREA = 351.36 351.54 699.84 699.3
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export MAX_ROUTING_LAYER = TopMetal2
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export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl
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export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.tcl
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export BLOCKS = I2cDeviceCtrl

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