yosys mapping files added for gf180

Signed-off-by: vijayank88 <[email protected]>

Author: vijayank88

flow/platforms/gf180/cells_adders.v

@@ -0,0 +1,48 @@
+
+(* techmap_celltype = "$fa" *)
+module _tech_fa (A, B, C, X, Y);
+  parameter WIDTH = 1;
+  (* force_downto *)
+    input [WIDTH-1 : 0] A, B, C;
+  (* force_downto *)
+    output [WIDTH-1 : 0] X, Y;
+  
+  parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
+  parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
+  parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;
+  
+  genvar i;
+  generate for (i = 0; i < WIDTH; i = i + 1) begin
+      if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
+        if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
+          gf180mcu_fd_sc_mcu9t5v0__addh_1 halfadder_Cconst (
+              .A(A[i]),
+              .B(B[i]),
+              .CO(X[i]), .S(Y[i])
+            );
+        end 
+        else begin
+          if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
+            gf180mcu_fd_sc_mcu9t5v0__addh_1 halfadder_Bconst (
+                .A(A[i]),
+                .B(C[i]),
+                .CO(X[i]), .S(Y[i])
+              );
+          end
+          else begin
+            gf180mcu_fd_sc_mcu9t5v0__addh_1 halfadder_Aconst (
+                .A(B[i]),
+                .B(C[i]),
+                .CO(X[i]), .S(Y[i])
+              );
+          end
+        end
+      end
+      else begin
+        gf180mcu_fd_sc_mcu9t5v0__addf_1 fulladder (
+            .A(A[i]), .B(B[i]), .CIN(C[i]), .CO(X[i]), .S(Y[i])
+          );
+      end
+    end endgenerate
+
+endmodule

flow/platforms/gf180/cells_latch.v

@@ -0,0 +1,15 @@
+module $_DLATCH_P_(input E, input D, output Q);
+    gf180mcu_fd_sc_mcu9t5v0__latq_1 _TECHMAP_REPLACE_ (
+        .D(D),
+        .E(E),
+        .Q(Q)
+        );
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+    gf180mcu_fd_sc_mcu9t5v0__latsnq_1 _TECHMAP_REPLACE_ (
+        .D(D),
+        .E(E),
+        .Q(Q)
+        );
+endmodule

flow/platforms/gf180/config.mk

@@ -55,6 +55,10 @@ export MIN_BUF_CELL_AND_PORTS                 = gf180mcu_fd_sc_mcu$(TRACK_OPTION
 # Used in synthesis
 export MAX_FANOUT                             = 20
 
+# Yosys mapping files
+export LATCH_MAP_FILE = $(PLATFORM_DIR)/cells_latch.v
+export ADDER_MAP_FILE = $(PLATFORM_DIR)/cells_adders.v
+
 #--------------------------------------------------------
 # Floorplan
 #-------------------------------------------------------