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lines changed Original file line number Diff line number Diff line change @@ -16,5 +16,3 @@ export CORE_AREA = 1.26 1.89 248 248
1616
1717
1818export PLACE_DENSITY = uniform
19-
20- export ABC_CLOCK_PERIOD_IN_PS = 2600
Original file line number Diff line number Diff line change @@ -11,11 +11,7 @@ export PLATFORM = intel22
1111export VERILOG_FILES = $(sort $(wildcard $(abspath $(DESIGN_HOME ) /src/$(DESIGN ) ) /* .v) )
1212export SDC_FILE = $(DESIGN_DIR ) /constraint.sdc
1313
14- export ABC_CLOCK_PERIOD_IN_PS = 400
15-
1614export PLACE_DENSITY = 0.35
1715
1816export DIE_AREA = 0 0 50 50
1917export CORE_AREA = 1.26 1.89 49 49
20-
21- export DESIGN_DIR DESIGN_PDK_HOME
Original file line number Diff line number Diff line change @@ -14,5 +14,3 @@ export CORE_ASPECT_RATIO = 1
1414export CORE_MARGIN = 2
1515
1616export PLACE_DENSITY = uniform
17-
18- export ABC_CLOCK_PERIOD_IN_PS = 8000
Original file line number Diff line number Diff line change @@ -15,5 +15,3 @@ export CORE_ASPECT_RATIO = 1
1515export CORE_MARGIN = 2
1616
1717export PLACE_DENSITY = uniform
18-
19- export ABC_CLOCK_PERIOD_IN_PS = 3800
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