Merge pull request #1121 from vijayank88/gf180_tc2

GF180 test case added

Author: maliberty

flow/Makefile

@@ -86,6 +86,8 @@
 # DESIGN_CONFIG=./designs/gf180/aes/config.mk
 # DESIGN_CONFIG=./designs/gf180/ibex/config.mk
 # DESIGN_CONFIG=./designs/gf180/jpeg/config.mk
+# DESIGN_CONFIG=./designs/gf180/riscv32i/config.mk
+# DESIGN_CONFIG=./designs/gf180/sha3/config.mk
 #
 # Default design
 DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk

flow/designs/gf180/riscv32i/config.mk

@@ -0,0 +1,12 @@
+export DESIGN_NICKNAME = riscv32i
+export DESIGN_NAME = riscv
+export PLATFORM    = gf180
+
+export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
+export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export CORE_UTILIZATION = 45
+export PLACE_DENSITY_LB_ADDON = 0.2
+export TNS_END_PERCENT = 100
+export HAS_IO_CONSTRAINTS = 1
+export PLACE_PINS_ARGS    = -min_distance 5 -exclude bottom:* -exclude top:*

flow/designs/gf180/riscv32i/constraint.sdc

@@ -0,0 +1,12 @@
+set clk_name  clk
+set clk_port_name clk
+set clk_period 10.0 
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/gf180/riscv32i/metadata-base-ok.json

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flow/designs/gf180/riscv32i/rules-base.json

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