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oharboejbylicki
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bazel: MockArray configuration
Signed-off-by: Øyvind Harboe <[email protected]>
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flow/BUILD.bazel

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@@ -104,3 +104,168 @@ orfs_flow(
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"final": all_sources,
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},
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)
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filegroup(
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name = "mock-array-constraints",
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srcs = [
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"designs/asap7/mock-array/constraints.sdc",
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],
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visibility = [":__subpackages__"],
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)
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filegroup(
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name = "mock-array-io",
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srcs = [
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"designs/asap7/mock-array/io.tcl"
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],
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data = [
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"designs/src/mock-array/util.tcl",
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],
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visibility = [":__subpackages__"],
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)
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filegroup(
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name = "mock-array-fastroute",
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srcs = [
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"designs/asap7/mock-array/fastroute.tcl",
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],
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visibility = [":__subpackages__"],
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)
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MOCK_ARRAY_ALL = {
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}
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MOCK_ARRAY_FLOORPLAN_PLACE = {
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"PLACE_PINS_ARGS": "-annealing",
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"IO_CONSTRAINTS": "$(location :mock-array-io)",
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"PLACE_DENSITY": "0.30",
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"DIE_AREA": "0 0 358.56 388.8",
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"CORE_AREA": "2.16 2.16 356.40000000000003 386.64000000000004",
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"MACRO_PLACE_HALO": "0 2.16",
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"RTLMP_BOUNDARY_WT": "0",
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"RTLMP_FLOW": "1",
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"PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl",
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"MACRO_HALO_X": "0.5",
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"MACRO_HALO_Y": "0.5",
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"MACRO_BLOCKAGE_HALO": "0",
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"ADDITIONAL_FILES": "$(locations :mock-array-io)",
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}
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orfs_flow(
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name = "MockArray",
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macros = ["Element_generate_abstract"],
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stage_args = {
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"synth": MOCK_ARRAY_ALL | {
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"SDC_FILE": "$(location :mock-array-constraints)",
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},
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"floorplan": MOCK_ARRAY_ALL | MOCK_ARRAY_FLOORPLAN_PLACE | {
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},
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"place": MOCK_ARRAY_ALL | MOCK_ARRAY_FLOORPLAN_PLACE | {
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},
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"cts": MOCK_ARRAY_ALL | {
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"CTS_BUF_DISTANCE": "60"
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},
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"route": MOCK_ARRAY_ALL | {
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"FASTROUTE_TCL": "$(location :mock-array-fastroute)",
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# works with 28 or more iterations as of writing, so give it a few more.
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"GLOBAL_ROUTE_ARGS" : "-congestion_iterations 40 -verbose",
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# If this design isn't quickly done in detailed routing, something is wrong.
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# At time of adding this option, only 12 iterations were needed for 0
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# violations.
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"DETAILED_ROUTE_ARGS": "-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 15",
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# since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
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# same information to other stages in the flow.
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"MIN_ROUTING_LAYER": "M2",
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"MAX_ROUTING_LAYER": "M7",
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},
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"final": MOCK_ARRAY_ALL | {
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"GDS_ALLOW_EMPTY": "Element",
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"PWR_NETS_VOLTAGEsS": "",
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"GND_NETS_VOLTAGES": "",
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}
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},
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verilog_files = glob(include=["designs/src/mock-array/*.v"]),
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stage_sources = {
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"synth": all_sources + [":mock-array-constraints"] + [":mock-array-io"],
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"floorplan": all_sources + [":mock-array-io"],
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"place": all_sources + [":mock-array-io"],
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"cts": all_sources,
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"route": all_sources + [":mock-array-fastroute"],
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"final": all_sources,
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},
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)
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filegroup(
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name = "mock-array-element-io",
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srcs = [
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"designs/asap7/mock-array/Element/io.tcl"
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],
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data = [
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"designs/src/mock-array/util.tcl",
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],
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visibility = [":__subpackages__"],
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)
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MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE = {
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"IO_CONSTRAINTS": "$(location :mock-array-element-io)",
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"PLACE_DENSITY": "0.50",
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"PLACE_PINS_ARGS": "-annealing",
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}
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MOCK_ARRAY_ELEMENT_ALL = {
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"MOCK_ARRAY_ROWS" : "8",
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"MOCK_ARRAY_COLS" : "8",
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}
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mock_array_all_sources = ["designs/src/mock-array/util.tcl"]
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orfs_flow(
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name = "Element",
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abstract_stage = "route",
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stage_args = {
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"synth": MOCK_ARRAY_ELEMENT_ALL | {
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"SDC_FILE": "$(location :mock-array-constraints)",
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},
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"floorplan": MOCK_ARRAY_ELEMENT_ALL | MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE | {
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"DIE_AREA": "0 0 43.2 43.2",
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"CORE_AREA": "1.08 1.08 42.120000000000005 42.120000000000005",
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"PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl",
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},
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"place": MOCK_ARRAY_ELEMENT_ALL | MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE | {
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},
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"cts": MOCK_ARRAY_ELEMENT_ALL | {
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},
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"route": MOCK_ARRAY_ELEMENT_ALL | {
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# If this design isn't quickly done in detailed routing, something is wrong.
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# At time of adding this option, only 3 iterations were needed for 0
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# violations.
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"DETAILED_ROUTE_ARGS": "-bottom_routing_layer M2 -top_routing_layer M5 -save_guide_updates -verbose 1 -droute_end_iter 10",
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# since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
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# same information to other stages in the flow.
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"MIN_ROUTING_LAYER": "M2",
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"MAX_ROUTING_LAYER": "M5",
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},
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"final": MOCK_ARRAY_ELEMENT_ALL | {
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"PWR_NETS_VOLTAGES": "",
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"GND_NETS_VOLTAGES": "",
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}
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},
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verilog_files = glob(include=["designs/src/mock-array/*.v"]),
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stage_sources = {
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"synth": mock_array_all_sources + [":mock-array-constraints"],
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"floorplan": mock_array_all_sources + [":mock-array-element-io"],
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"place": mock_array_all_sources + [":mock-array-element-io"],
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"cts": mock_array_all_sources,
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"route": mock_array_all_sources + [":mock-array-fastroute"],
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"final": mock_array_all_sources,
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},
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)
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