Merge remote-tracking branch 'origin/master' into secure-remove_random_ppl

eder-matheus · eder-matheus · commit f1b28047d49f · 2025-03-18T22:56:41.000-03:00
Signed-off-by: Eder Monteiro &lt;emrmonteiro@precisioninno.com&gt;
diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 1100 
+set clk_period 900
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -71.1,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/asap7/riscv32i-mock-sram/io.tcl b/flow/designs/asap7/riscv32i-mock-sram/io.tcl
@@ -0,0 +1 @@
+exclude_io_pin_region -region left:* -region right:* -region top:*
diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 6 
+set clk_period 6
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc
@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 10.75
+set clk_period 10.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.43,
+        "value": -1.03,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 10.0 
+set clk_period 6.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json
@@ -28,43 +28,43 @@
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 322,
+        "value": 310,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 771955,
+        "value": 771195,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__antenna__violating__nets": {
-        "value": 16,
+        "value": 14,
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
         "value": 5,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.98,
         "compare": ">="
     },
     "finish__design__instance__area": {
         "value": 411968,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 10,
+        "value": 523,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 10,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -24.94,
         "compare": ">="
     }
 }
diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json
@@ -60,7 +60,7 @@
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 1792,
+        "value": 309,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 1.4 
+set clk_period 1.2
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.04,
+        "value": -0.17,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 7.5 
+set clk_period 5.5
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json
@@ -8,11 +8,11 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 498519,
+        "value": 497902,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 55316,
+        "value": 55309,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -28,27 +28,27 @@
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 208,
+        "value": 402,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1211683,
+        "value": 1397876,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__antenna__violating__nets": {
-        "value": 1,
+        "value": 0,
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
         "value": 166,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.5,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc
@@ -2,7 +2,7 @@ current_design aes_cipher_top
 
 set clk_name  clk
 set clk_port_name clk
-set clk_period 4.0 
+set clk_period 3.1
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json
@@ -28,11 +28,11 @@
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 64,
+        "value": 128,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 688847,
+        "value": 794664,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -44,15 +44,15 @@
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
-        "value": 28,
+        "value": 50,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.07,
+        "value": -0.23,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 186844,
+        "value": 223122,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc
@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 11.8 
+set clk_period 9.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json
@@ -28,7 +28,7 @@
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 2,
+        "value": 8,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
@@ -44,7 +44,7 @@
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
-        "value": 21,
+        "value": 33,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 7.6 
+set clk_period 5.2
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.52,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/jenkins/public_nightly.Jenkinsfile b/jenkins/public_nightly.Jenkinsfile
@@ -1,4 +1,4 @@
-@Library('utils@orfs-v2.3.0') _
+@Library('utils@orfs-v2.3.1') _
 
 node {
 
diff --git a/jenkins/public_tests_all.Jenkinsfile b/jenkins/public_tests_all.Jenkinsfile
@@ -1,4 +1,4 @@
-@Library('utils@orfs-v2.3.0') _
+@Library('utils@orfs-v2.3.1') _
 
 node {
 

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1 @@`
	`1`	`+exclude_io_pin_region -region left:* -region right:* -region top:*`