Skip to content

Commit f2a26d7

Browse files
committed
chore(designs): Increase precision of values.
e.g., "value" : -0.03 -> -0.0373 Before this change, low precision TNS value (e.g., -0.03) caused metadata check fail when the actual value is -0.0311. Increasing the precision resolves the issue. Updated `rules-base.json` files. Signed-off-by: Jaehyun Kim <[email protected]>
1 parent 4bfde6c commit f2a26d7

File tree

25 files changed

+29
-29
lines changed

25 files changed

+29
-29
lines changed

flow/designs/asap7/cva6/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 18784.42,
3+
"value": 18784.4143,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/ethmac/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 8468.2,
3+
"value": 8468.1902,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/ethmac_lvt/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 8418.68,
3+
"value": 8418.6772,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/gcd-ccs/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 43.11,
3+
"value": 43.108,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/gcd/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 43.11,
3+
"value": 43.108,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/jpeg_lvt/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 7047.58,
3+
"value": 7047.5726,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/riscv32i-mock-sram/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 1640.79,
3+
"value": 1640.7857,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/asap7/riscv32i/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 2908.69,
3+
"value": 2908.6846,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/gf180/aes-hybrid/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 489779.42,
3+
"value": 489779.4138,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

flow/designs/gf180/aes/rules-base.json

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 620261.5,
3+
"value": 620261.4903,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {

0 commit comments

Comments
 (0)