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1 parent 39a7e6d commit f33a5ebCopy full SHA for f33a5eb
flow/designs/gf12/swerv_wrapper/config.mk
@@ -4,12 +4,6 @@ export PLATFORM = gf12
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export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
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export SYNTH_HIERARCHICAL = 1
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-# RTL_MP Settings
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-export RTLMP_MAX_INST = 25000
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-export RTLMP_MIN_INST = 5000
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-export RTLMP_MAX_MACRO = 12
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-export RTLMP_MIN_MACRO = 4
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-
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export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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