|
| 1 | +load("@bazel-orfs//:openroad.bzl", "orfs_flow") |
| 2 | + |
| 3 | +filegroup( |
| 4 | + name = "constraints-gcd", |
| 5 | + srcs = [ |
| 6 | + "designs/asap7/gcd/constraint.sdc", |
| 7 | + ], |
| 8 | + visibility = [":__subpackages__"], |
| 9 | +) |
| 10 | + |
| 11 | +orfs_flow( |
| 12 | + name = "gcd", |
| 13 | + stage_args = { |
| 14 | + "synth": { |
| 15 | + "SDC_FILE": "$(location :constraints-gcd)", |
| 16 | + }, |
| 17 | + "floorplan": { |
| 18 | + "DIE_AREA": "0 0 16.2 16.2", |
| 19 | + "CORE_AREA": "1.08 1.08 15.12 15.12", |
| 20 | + }, |
| 21 | + "place": { |
| 22 | + "PLACE_DENSITY": "0.35", |
| 23 | + }, |
| 24 | + }, |
| 25 | + stage_sources = { |
| 26 | + "synth": [":constraints-gcd"], |
| 27 | + }, |
| 28 | + verilog_files = glob(include=["designs/src/gcd/*.v"]), |
| 29 | +) |
| 30 | + |
| 31 | + |
| 32 | +filegroup( |
| 33 | + name = "constraints-swerv", |
| 34 | + srcs = [ |
| 35 | + "designs/asap7/swerv_wrapper/constraint.sdc", |
| 36 | + ], |
| 37 | + visibility = [":__subpackages__"], |
| 38 | +) |
| 39 | + |
| 40 | +filegroup( |
| 41 | + name = "swerv-fastroute", |
| 42 | + srcs = [ |
| 43 | + "designs/asap7/swerv_wrapper/fastroute.tcl", |
| 44 | + ], |
| 45 | + visibility = [":__subpackages__"], |
| 46 | +) |
| 47 | + |
| 48 | +filegroup( |
| 49 | + name = "additional_lefs", |
| 50 | + srcs = glob(include=["designs/asap7/swerv_wrapper/lef/*.lef"]) |
| 51 | +) |
| 52 | +filegroup( |
| 53 | + name = "additional_libs", |
| 54 | + srcs = glob(include=["designs/asap7/swerv_wrapper/lib/*.lib"]) |
| 55 | +) |
| 56 | + |
| 57 | +SWERV_ALL = { |
| 58 | + "LIB_MODEL":"CCS", |
| 59 | + "ADDITIONAL_LEFS": "$(locations :additional_lefs)", |
| 60 | + "ADDITIONAL_LIBS": "$(locations :additional_libs)", |
| 61 | +} |
| 62 | + |
| 63 | +all_sources = [":additional_lefs", ":additional_libs"] |
| 64 | + |
| 65 | +orfs_flow( |
| 66 | + name = "swerv_wrapper", |
| 67 | + stage_args = { |
| 68 | + "synth": SWERV_ALL | { |
| 69 | + "SYNTH_HIERARCHICAL": "1", |
| 70 | + "SDC_FILE": "$(location :constraints-swerv)", |
| 71 | + }, |
| 72 | + "floorplan": SWERV_ALL | { |
| 73 | + "RTLMP_FLOW": "1", |
| 74 | + "RTLMP_MAX_INST": "30000", |
| 75 | + "RTLMP_MIN_INST": "5000", |
| 76 | + "RTLMP_MAX_MACRO": "30", |
| 77 | + "RTLMP_MIN_MACRO": "4", |
| 78 | + "DIE_AREA": "0 0 550 600", |
| 79 | + "CORE_AREA": "5 5 545 595", |
| 80 | + "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*" |
| 81 | + }, |
| 82 | + "place": SWERV_ALL | { |
| 83 | + "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*", |
| 84 | + "PLACE_DENSITY_LB_ADDON": "0.20", |
| 85 | + }, |
| 86 | + "cts": SWERV_ALL | { |
| 87 | + "TNS_END_PERCENT": "100", |
| 88 | + }, |
| 89 | + "route": SWERV_ALL | { |
| 90 | + "FASTROUTE_TCL": "$(location :swerv-fastroute)", |
| 91 | + }, |
| 92 | + "final": SWERV_ALL | { |
| 93 | + "PWR_NETS_VOLTAGEsS": "", |
| 94 | + "GND_NETS_VOLTAGES": "", |
| 95 | + } |
| 96 | + }, |
| 97 | + verilog_files = glob(include=[ |
| 98 | + "designs/src/swerv/swerv_wrapper.sv2v.v", |
| 99 | + "designs/asap7/swerv_wrapper/macros.v" |
| 100 | + ]), |
| 101 | + stage_sources = { |
| 102 | + "synth": all_sources + [":constraints-swerv"], |
| 103 | + "floorplan": all_sources, |
| 104 | + "place": all_sources, |
| 105 | + "cts": all_sources, |
| 106 | + "route": all_sources + [":swerv-fastroute"], |
| 107 | + "final": all_sources, |
| 108 | + }, |
| 109 | +) |
| 110 | + |
| 111 | + |
| 112 | +filegroup( |
| 113 | + name = "mock-array-constraints", |
| 114 | + srcs = [ |
| 115 | + "designs/asap7/mock-array/constraints.sdc", |
| 116 | + ], |
| 117 | + visibility = [":__subpackages__"], |
| 118 | +) |
| 119 | + |
| 120 | +filegroup( |
| 121 | + name = "mock-array-io", |
| 122 | + srcs = [ |
| 123 | + "designs/asap7/mock-array/io.tcl" |
| 124 | + ], |
| 125 | + data = [ |
| 126 | + "designs/src/mock-array/util.tcl", |
| 127 | + ], |
| 128 | + visibility = [":__subpackages__"], |
| 129 | +) |
| 130 | + |
| 131 | +filegroup( |
| 132 | + name = "mock-array-fastroute", |
| 133 | + srcs = [ |
| 134 | + "designs/asap7/mock-array/fastroute.tcl", |
| 135 | + ], |
| 136 | + visibility = [":__subpackages__"], |
| 137 | +) |
| 138 | + |
| 139 | +MOCK_ARRAY_FLOORPLAN_PLACE = { |
| 140 | + "PLACE_PINS_ARGS": "-annealing", |
| 141 | + "IO_CONSTRAINTS": "$(location :mock-array-io)", |
| 142 | + "PLACE_DENSITY": "0.30", |
| 143 | + "DIE_AREA": "0 0 358.56 388.8", |
| 144 | + "CORE_AREA": "2.16 2.16 356.40000000000003 386.64000000000004", |
| 145 | + "MACRO_PLACE_HALO": "0 2.16", |
| 146 | + "RTLMP_BOUNDARY_WT": "0", |
| 147 | + "RTLMP_FLOW": "1", |
| 148 | + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", |
| 149 | + "MACRO_HALO_X": "0.5", |
| 150 | + "MACRO_HALO_Y": "0.5", |
| 151 | + "MACRO_BLOCKAGE_HALO": "0", |
| 152 | + "ADDITIONAL_FILES": "$(locations :mock-array-io)", |
| 153 | +} |
| 154 | + |
| 155 | +orfs_flow( |
| 156 | + name = "MockArray", |
| 157 | + macros = ["Element_generate_abstract"], |
| 158 | + stage_args = { |
| 159 | + "synth": { |
| 160 | + "SDC_FILE": "$(location :mock-array-constraints)", |
| 161 | + }, |
| 162 | + "floorplan": MOCK_ARRAY_FLOORPLAN_PLACE | { |
| 163 | + }, |
| 164 | + "place": MOCK_ARRAY_FLOORPLAN_PLACE | { |
| 165 | + }, |
| 166 | + "cts": { |
| 167 | + "CTS_BUF_DISTANCE": "60" |
| 168 | + }, |
| 169 | + "route": { |
| 170 | + "FASTROUTE_TCL": "$(location :mock-array-fastroute)", |
| 171 | + # works with 28 or more iterations as of writing, so give it a few more. |
| 172 | + "GLOBAL_ROUTE_ARGS" : "-congestion_iterations 40 -verbose", |
| 173 | + # If this design isn't quickly done in detailed routing, something is wrong. |
| 174 | + # At time of adding this option, only 12 iterations were needed for 0 |
| 175 | + # violations. |
| 176 | + "DETAILED_ROUTE_ARGS": "-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 15", |
| 177 | + # since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the |
| 178 | + # same information to other stages in the flow. |
| 179 | + "MIN_ROUTING_LAYER": "M2", |
| 180 | + "MAX_ROUTING_LAYER": "M7", |
| 181 | + }, |
| 182 | + "final": { |
| 183 | + "GDS_ALLOW_EMPTY": "Element", |
| 184 | + "PWR_NETS_VOLTAGEsS": "", |
| 185 | + "GND_NETS_VOLTAGES": "", |
| 186 | + } |
| 187 | + }, |
| 188 | + verilog_files = glob(include=["designs/src/mock-array/*.v"]), |
| 189 | + stage_sources = { |
| 190 | + "synth": all_sources + [":mock-array-constraints"] + [":mock-array-io"], |
| 191 | + "floorplan": all_sources + [":mock-array-io"], |
| 192 | + "place": all_sources + [":mock-array-io"], |
| 193 | + "cts": all_sources, |
| 194 | + "route": all_sources + [":mock-array-fastroute"], |
| 195 | + "final": all_sources, |
| 196 | + }, |
| 197 | +) |
| 198 | + |
| 199 | + |
| 200 | +filegroup( |
| 201 | + name = "mock-array-element-io", |
| 202 | + srcs = [ |
| 203 | + "designs/asap7/mock-array/Element/io.tcl" |
| 204 | + ], |
| 205 | + data = [ |
| 206 | + "designs/src/mock-array/util.tcl", |
| 207 | + ], |
| 208 | + visibility = [":__subpackages__"], |
| 209 | +) |
| 210 | + |
| 211 | +MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE = { |
| 212 | + "IO_CONSTRAINTS": "$(location :mock-array-element-io)", |
| 213 | + "PLACE_DENSITY": "0.50", |
| 214 | + "PLACE_PINS_ARGS": "-annealing", |
| 215 | +} |
| 216 | + |
| 217 | +MOCK_ARRAY_ELEMENT_ALL = { |
| 218 | +"MOCK_ARRAY_ROWS" : "8", |
| 219 | +"MOCK_ARRAY_COLS" : "8", |
| 220 | +} |
| 221 | + |
| 222 | +mock_array_all_sources = ["designs/src/mock-array/util.tcl"] |
| 223 | + |
| 224 | +orfs_flow( |
| 225 | + name = "Element", |
| 226 | + abstract_stage = "route", |
| 227 | + stage_args = { |
| 228 | + "synth": MOCK_ARRAY_ELEMENT_ALL | { |
| 229 | + "SDC_FILE": "$(location :mock-array-constraints)", |
| 230 | + }, |
| 231 | + "floorplan": MOCK_ARRAY_ELEMENT_ALL | MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE | { |
| 232 | + "DIE_AREA": "0 0 43.2 43.2", |
| 233 | + "CORE_AREA": "1.08 1.08 42.120000000000005 42.120000000000005", |
| 234 | + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl", |
| 235 | + }, |
| 236 | + "place": MOCK_ARRAY_ELEMENT_ALL | MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE | { |
| 237 | + }, |
| 238 | + "cts": MOCK_ARRAY_ELEMENT_ALL | { |
| 239 | + }, |
| 240 | + "route": MOCK_ARRAY_ELEMENT_ALL | { |
| 241 | + # If this design isn't quickly done in detailed routing, something is wrong. |
| 242 | + # At time of adding this option, only 3 iterations were needed for 0 |
| 243 | + # violations. |
| 244 | + "DETAILED_ROUTE_ARGS": "-bottom_routing_layer M2 -top_routing_layer M5 -save_guide_updates -verbose 1 -droute_end_iter 10", |
| 245 | + # since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the |
| 246 | + # same information to other stages in the flow. |
| 247 | + "MIN_ROUTING_LAYER": "M2", |
| 248 | + "MAX_ROUTING_LAYER": "M5", |
| 249 | + }, |
| 250 | + "final": MOCK_ARRAY_ELEMENT_ALL | { |
| 251 | + "PWR_NETS_VOLTAGES": "", |
| 252 | + "GND_NETS_VOLTAGES": "", |
| 253 | + } |
| 254 | + }, |
| 255 | + verilog_files = glob(include=["designs/src/mock-array/*.v"]), |
| 256 | + stage_sources = { |
| 257 | + "synth": mock_array_all_sources + [":mock-array-constraints"], |
| 258 | + "floorplan": mock_array_all_sources + [":mock-array-element-io"], |
| 259 | + "place": mock_array_all_sources + [":mock-array-element-io"], |
| 260 | + "cts": mock_array_all_sources, |
| 261 | + "route": mock_array_all_sources + [":mock-array-fastroute"], |
| 262 | + "final": mock_array_all_sources, |
| 263 | + }, |
| 264 | +) |
| 265 | + |
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