synth: Rm .lib preprocess after tools improved

povik · povik · commit f4a2f41b2a26 · 2025-08-21T16:10:21.000+02:00
Signed-off-by: Martin Povišer &lt;povik@cutebit.org&gt;
diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
@@ -126,7 +126,6 @@ configuration file.
 | <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| |
 | <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
 | <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
-| <a name="DONT_USE_LIBS"></a>DONT_USE_LIBS| Set liberty files as `dont_use`.| |
 | <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1|
 | <a name="EARLY_SIZING_CAP_RATIO"></a>EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| |
 | <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1|
@@ -459,7 +458,6 @@ configuration file.
 - [DESIGN_NICKNAME](#DESIGN_NICKNAME)
 - [DFF_LIB_FILES](#DFF_LIB_FILES)
 - [DONT_USE_CELLS](#DONT_USE_CELLS)
-- [DONT_USE_LIBS](#DONT_USE_LIBS)
 - [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT)
 - [ENABLE_DPO](#ENABLE_DPO)
 - [FASTROUTE_TCL](#FASTROUTE_TCL)
diff --git a/flow/Makefile b/flow/Makefile
@@ -188,19 +188,6 @@ versions.txt:
 	@echo "openroad $(if $(OPENROAD_EXE),$(shell $(OPENROAD_EXE) -version 2>&1),not available)" >> $(OBJECTS_DIR)/$@
 	@echo "klayout $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -zz -v 2>&1),not available)" >> $(OBJECTS_DIR)/$@
 
-# Pre-process libraries
-# ==============================================================================
-
-# Create temporary Liberty files which have the proper dont_use properties set
-# For use with Yosys and ABC
-.SECONDEXPANSION:
-$(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
-	@mkdir -p $(OBJECTS_DIR)/lib
-	$(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@
-
-$(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS)
-	$(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
-
 # Pre-process KLayout tech
 # ==============================================================================
 $(OBJECTS_DIR)/klayout_tech.lef: $(TECH_LEF)
@@ -281,11 +268,11 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
 yosys-dependencies: $(YOSYS_DEPENDENCIES)
 
 .PHONY: do-yosys
-do-yosys: $(DONT_USE_SC_LIB)
+do-yosys: yosys-dependencies
 	$(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log
 
 .PHONY: do-yosys-canonicalize
-do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB)
+do-yosys-canonicalize: yosys-dependencies
 	$(SCRIPTS_DIR)/synth.sh $(SCRIPTS_DIR)/synth_canonicalize.tcl $(LOG_DIR)/1_1_yosys_canonicalize.log
 
 $(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil: $(YOSYS_DEPENDENCIES)
@@ -416,7 +403,7 @@ endef
 
 $(eval $(call do-step,1_3_synth,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc,synth_odb))
 
-$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(DONT_USE_SC_LIB),floorplan))
+$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(LIB_FILES),floorplan))
 
 $(eval $(call do-copy,2_floorplan,2_1_floorplan.sdc,,.sdc))
 
diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk
@@ -201,11 +201,6 @@ export DB_FILES              += $(realpath $($(CORNER)_DB_FILES))
 export TEMPERATURE            = $($(CORNER)_TEMPERATURE)
 export VOLTAGE                = $($(CORNER)_VOLTAGE)
 
-# FIXME Need merged.lib for now, but ideally it shouldn't be necessary:
-#
-# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/2139
-export DONT_USE_SC_LIB        = $(OBJECTS_DIR)/lib/merged.lib
-
 # ---------------------------------------------------------
 #  IR Drop
 # ---------------------------------------------------------
diff --git a/flow/platforms/asap7/openRoad/post_mergeLib.py b/flow/platforms/asap7/openRoad/post_mergeLib.py
diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl
@@ -103,17 +103,12 @@ if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } {
   techmap -map $::env(LATCH_MAP_FILE)
 }
 
-set dfflibmap_args ""
-foreach cell $::env(DONT_USE_CELLS) {
-  lappend dfflibmap_args -dont_use $cell
-}
-
 # Technology mapping of flip-flops
 # dfflibmap only supports one liberty file
 if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
-  dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
+  dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$lib_dont_use_args
 } else {
-  dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
+  dfflibmap {*}$lib_args {*}$lib_dont_use_args
 }
 opt
 
@@ -147,7 +142,7 @@ insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS)
 # Reports
 tee -o $::env(REPORTS_DIR)/synth_check.txt check
 
-tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
+tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$lib_args
 
 # check the design is composed exclusively of target cells, and check for other problems
 if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl
@@ -94,20 +94,25 @@ if { $::env(ABC_AREA) } {
   set abc_script $::env(SCRIPTS_DIR)/abc_speed.script
 }
 
-# Technology mapping for cells
-# ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't
-set abc_args [list -script $abc_script \
-  -liberty $::env(DONT_USE_SC_LIB) \
-  -constr $::env(OBJECTS_DIR)/abc.constr]
+# Create argument list for stat
+set lib_args ""
+foreach lib $::env(LIB_FILES) {
+  append lib_args "-liberty $lib "
+}
 
 # Exclude dont_use cells. This includes macros that are specified via
 # LIB_FILES and ADDITIONAL_LIBS that are included in LIB_FILES.
+set lib_dont_use_args ""
 if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
   foreach cell $::env(DONT_USE_CELLS) {
-    lappend abc_args -dont_use $cell
+    lappend lib_dont_use_args -dont_use $cell
   }
 }
 
+# Technology mapping for cells
+set abc_args [list -script $abc_script \
+  {*}$lib_args {*}$lib_dont_use_args -constr $::env(OBJECTS_DIR)/abc.constr]
+
 if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } {
   puts "Extracting clock period from SDC file: $::env(SDC_FILE_CLOCK_PERIOD)"
   set fp [open $::env(SDC_FILE_CLOCK_PERIOD) r]
@@ -119,12 +124,6 @@ if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } {
   close $fp
 }
 
-# Create argument list for stat
-set stat_libs ""
-foreach lib $::env(DONT_USE_LIBS) {
-  append stat_libs "-liberty $lib "
-}
-
 set constr [open $::env(OBJECTS_DIR)/abc.constr w]
 puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)"
 puts $constr "set_load $::env(ABC_LOAD_IN_FF)"
diff --git a/flow/scripts/synth_stdcells.tcl b/flow/scripts/synth_stdcells.tcl
@@ -1,5 +1,4 @@
 # Read standard cells and macros as blackbox inputs
-# These libs have their dont_use properties set accordingly
-read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(DONT_USE_LIBS)
+read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(LIB_FILES)
 read_liberty -overwrite -setattr liberty_cell \
-  -unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS)
+  -unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(LIB_FILES)
diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk
@@ -132,9 +132,6 @@ WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_m
 export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS)
 export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS)
 
-export DONT_USE_LIBS   = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES))))
-export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS))
-
 # Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS
 STREAM_SYSTEM ?= GDS
 ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),)
@@ -163,7 +160,7 @@ export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH)
 export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
 export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
 
-export YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
+export YOSYS_DEPENDENCIES=$(LIB_FILES) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
 
 # Ubuntu 22.04 ships with older than 0.28.11, so support older versions
 # for a while still.
diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml
@@ -705,9 +705,6 @@ CDL_FILES:
 DFF_LIB_FILES:
   description: |
     Technology mapping liberty files for flip-flops.
-DONT_USE_LIBS:
-  description: |
-    Set liberty files as `dont_use`.
 SYNTH_KEEP_MODULES:
   description: |
     Mark modules to keep from getting removed in flattening.
diff --git a/flow/util/merge_lib.py b/flow/util/merge_lib.py
diff --git a/flow/util/preprocessLib.py b/flow/util/preprocessLib.py
