makefile: fix passing of variables on command line

fixes #1246

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/Makefile

@@ -895,6 +895,9 @@ handoff : all_defs all_verilog
 
 print-%  : ; @echo $* = $($*)
 
+.PHONY: test-unset-and-make-%
+test-unset-and-make-%: ; $(UNSET_AND_MAKE) $*
+
 # Utilities
 #-------------------------------------------------------------------------------
 include $(UTILS_DIR)/utils.mk

flow/util/utils.mk

@@ -85,7 +85,7 @@ define \n
 
 endef
 
-export ISSUE_VARIABLES_NAMES := $(foreach V, $(.VARIABLES),$(if $(filter-out environment% default automatic, $(origin $V)), $(if $(filter-out .% %QT_QPA_PLATFORM% %TIME_CMD% KLAYOUT% GENERATE_ABSTRACT_RULE%, $(V)), $V$ )))
+export ISSUE_VARIABLES_NAMES := $(foreach V, $(.VARIABLES),$(if $(filter-out command% line environment% default automatic, $(origin $V)), $(if $(filter-out .% %QT_QPA_PLATFORM% %TIME_CMD% KLAYOUT% GENERATE_ABSTRACT_RULE%, $(V)), $V$ )))
 export ISSUE_VARIABLES := $(foreach V, $(ISSUE_VARIABLES_NAMES), $(if $($V),$V=$($V),$V='')${\n})
 
 $(foreach script,$(ISSUE_SCRIPTS),$(script)_issue): %_issue : versions.txt