Merge pull request #2372 from Pinata-Consulting/makefile-less-iffy-fill-code

maliberty · web-flow · commit f54b1aaa50b3 · 2024-09-25T13:25:34.000Z
makefile: less iffy, less surprising fillcell code
diff --git a/flow/Makefile b/flow/Makefile
@@ -900,13 +900,7 @@ elapsed:
 elapsed-all:
 	@$(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d)
 
-# ==============================================================================
-
-ifeq ($(USE_FILL),1)
 $(eval $(call do-step,6_1_fill,$(RESULTS_DIR)/5_route.odb $(RESULTS_DIR)/5_route.sdc $(FILL_CONFIG),density_fill))
-else
-$(eval $(call do-copy,6_1_fill,5_route.odb))
-endif
 
 $(eval $(call do-copy,6_1_fill,5_route.sdc,,.sdc))
 
diff --git a/flow/designs/gf12/aes/config.mk b/flow/designs/gf12/aes/config.mk
@@ -12,7 +12,7 @@ export CORE_MARGIN       = 2
 
 export PLACE_DENSITY     = 0.80
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
@@ -30,7 +30,7 @@ export MACRO_PLACE_CHANNEL = 14 14
 
 export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk
@@ -27,7 +27,7 @@ export MACRO_PLACE_CHANNEL = 14 14
 
 export PLACE_DENSITY_LB_ADDON = 0.05
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk
@@ -63,7 +63,7 @@ export MACRO_BLOCKAGE_HALO = 25
 export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
 export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CHIP
 else
 export DESIGN_TYPE = CHIP_NODEN
diff --git a/flow/designs/gf12/ca53/config.mk b/flow/designs/gf12/ca53/config.mk
@@ -59,7 +59,7 @@ export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG))/wrappers.tcl
 #export MAX_ROUTING_LAYER = H2 
 export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute.tcl
 #
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/coyote/config.mk b/flow/designs/gf12/coyote/config.mk
@@ -31,7 +31,7 @@ export DIE_AREA    = 0 0 752 752
 export CORE_AREA   = 2 2 750 750
 export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-20 -exclude bottom:450-750
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/gcd/config.mk b/flow/designs/gf12/gcd/config.mk
@@ -11,7 +11,7 @@ export CORE_AREA   = 9.996 10.08 89.964 90.048
 
 export GLOBAL_PLACEMENT_ARGS = -skip_initial_place
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk
@@ -51,7 +51,7 @@ export CORE_MARGIN = 2
 
 export PLACE_DENSITY = 0.70
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/jpeg/config.mk b/flow/designs/gf12/jpeg/config.mk
@@ -14,7 +14,7 @@ export CORE_MARGIN = 2
 
 export PLACE_DENSITY = 0.75
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk
@@ -38,7 +38,7 @@ export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
 export MACRO_PLACE_HALO = 7 7
 export MACRO_PLACE_CHANNEL = 14 14
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk
@@ -34,7 +34,7 @@ export PLACE_DENSITY = 0.20
 
 export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf180/aes-hybrid/config.mk b/flow/designs/gf180/aes-hybrid/config.mk
@@ -35,7 +35,7 @@ export BALANCE_ROWS = 1
 
 export PDN_TCL = $(PLATFORM_DIR)/openROAD/pdn/pdn_grid_strategy_7t_6M.cfg
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf180/aes/config.mk b/flow/designs/gf180/aes/config.mk
@@ -12,7 +12,7 @@ export CORE_MARGIN       = 2
 
 export PLACE_DENSITY = 0.60
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/designs/gf55/aes/config.mk b/flow/designs/gf55/aes/config.mk
@@ -19,7 +19,7 @@ export CORE_MARGIN       = 4
 export PLACE_DENSITY     = 0.50
 export RECOVER_POWER     = 100
 
-ifneq ($(USE_FILL),)
+ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
diff --git a/flow/scripts/density_fill.tcl b/flow/scripts/density_fill.tcl
@@ -1,9 +1,14 @@
 source $::env(SCRIPTS_DIR)/load.tcl
 load_design 5_route.odb 5_route.sdc
 
-set_propagated_clock [all_clocks]
-
-density_fill -rules $::env(FILL_CONFIG)
-
-write_db $::env(RESULTS_DIR)/6_1_fill.odb
-write_verilog $::env(RESULTS_DIR)/6_1_fill.v
+if {[env_var_equals USE_FILL 1]} {
+  set_propagated_clock [all_clocks]
+  density_fill -rules $::env(FILL_CONFIG)
+  # The .v file is just for debugging purposes, not a result of
+  # this stage.
+  write_verilog $::env(RESULTS_DIR)/6_1_fill.v
+  write_db $::env(RESULTS_DIR)/6_1_fill.odb
+} else {
+  log_cmd exec cp $::env(RESULTS_DIR)/5_route.odb $::env(RESULTS_DIR)/6_1_fill.odb
+  # There is no 5_route.v file to copy
+}
diff --git a/flow/scripts/fillcell.tcl b/flow/scripts/fillcell.tcl
@@ -5,13 +5,12 @@ if {[expr [file exists $::env(REPORTS_DIR)/congestion.rpt] && \
 }
 
 source $::env(SCRIPTS_DIR)/load.tcl
-
 if {[env_var_exists_and_non_empty FILL_CELLS]} {
   load_design 5_2_route.odb 4_cts.sdc
 
   set_propagated_clock [all_clocks]
 
-  filler_placement $::env(FILL_CELLS)
+  log_cmd filler_placement $::env(FILL_CELLS)
   check_placement
 
   write_db $::env(RESULTS_DIR)/5_3_fillcell.odb

Original file line number	Diff line number	Diff line change
`@@ -59,7 +59,7 @@ export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG))/wrappers.tcl`
`59`	`59`	`#export MAX_ROUTING_LAYER = H2`
`60`	`60`	`export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute.tcl`
`61`	`61`	`#`
`62`		`-ifneq ($(USE_FILL),)`
	`62`	`+ifeq ($(USE_FILL),1)`
`63`	`63`	`export DESIGN_TYPE = CELL`
`64`	`64`	`else`
`65`	`65`	`export DESIGN_TYPE = CELL_NODEN`