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mock-alu: plot area and minimum period for various operations
Signed-off-by: Øyvind Harboe <[email protected]>
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-396
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18 files changed

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-396
lines changed

‎flow/designs/asap7/mock-alu/defaults.mk‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1 +1,2 @@
11
export MOCK_ALU_WIDTH ?= 64
2+
export MOCK_ALU_OPERATIONS?= ADD,SUB,AND,OR,XOR,SHL,SHR,SRA,SETCC_EQ,SETCC_NE,SETCC_LT,SETCC_ULT,SETCC_LE,SETCC_ULE,MULT

‎flow/designs/asap7/mock-alu/metadata-base-ok.json‎

Lines changed: 264 additions & 264 deletions
Large diffs are not rendered by default.

‎flow/designs/asap7/mock-alu/rules-base.json‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,11 +24,11 @@
2424
"compare": ">="
2525
},
2626
"cts__timing__setup__ws__pre_repair": {
27-
"value": -227.1,
27+
"value": -517.62,
2828
"compare": ">="
2929
},
3030
"cts__timing__setup__ws__post_repair": {
31-
"value": -188.74,
31+
"value": -517.62,
3232
"compare": ">="
3333
},
3434
"cts__design__instance__count__setup_buffer": {
@@ -40,11 +40,11 @@
4040
"compare": "<="
4141
},
4242
"globalroute__timing__clock__slack": {
43-
"value": -40.9,
43+
"value": -109.03,
4444
"compare": ">="
4545
},
4646
"globalroute__timing__setup__ws": {
47-
"value": -29.09,
47+
"value": -109.03,
4848
"compare": ">="
4949
},
5050
"detailedroute__route__wirelength": {
@@ -56,7 +56,7 @@
5656
"compare": "<="
5757
},
5858
"finish__timing__setup__ws": {
59-
"value": -50.05,
59+
"value": -100.67,
6060
"compare": ">="
6161
},
6262
"finish__design__instance__area": {
@@ -76,7 +76,7 @@
7676
"compare": ">="
7777
},
7878
"finish__timing__drv__setup_violation_count": {
79-
"value": 10,
79+
"value": 71,
8080
"compare": "<="
8181
},
8282
"finish__timing__drv__hold_violation_count": {

‎flow/designs/asap7/mock-alu/verilog.sh‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,10 @@ cd $DIR
99

1010
cd ../../src/mock-alu
1111

12+
rm -f *.v
13+
1214
sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
13-
"test:runMain GenerateMockAlu --width ${MOCK_ALU_WIDTH} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
15+
"test:runMain GenerateMockAlu --width ${MOCK_ALU_WIDTH} --operations ${MOCK_ALU_OPERATIONS} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
1416

1517
# reduce git noise as these comments will change if the line numbers in Chisel changes
1618
find . -name "*.v" -type f -exec sed -i 's/ \/\/.*$//' {} \;

‎flow/designs/src/mock-alu/BarrelShifter.v‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
11
module BarrelShifter(
22
input [63:0] io_data,
33
input [5:0] io_shiftAmount,
4-
input [3:0] io_dir,
4+
input [4:0] io_dir,
55
output [63:0] io_out
66
);
7-
wire _rotate_T = io_dir == 4'h5;
7+
wire _rotate_T = io_dir == 5'h8;
88
wire [6:0] _GEN_0 = {{1'd0}, io_shiftAmount};
99
wire [6:0] _rotate_T_2 = 7'h40 - _GEN_0;
1010
wire [6:0] rotate = _rotate_T ? _rotate_T_2 : {{1'd0}, io_shiftAmount};
1111
wire [63:0] _rotateInput_T_3 = io_data[63] ? 64'hffffffffffffffff : 64'h0;
12-
wire [63:0] _rotateInput_T_8 = 4'h7 == io_dir ? _rotateInput_T_3 : 64'h0;
13-
wire [63:0] _rotateInput_T_10 = 4'h5 == io_dir ? io_data : _rotateInput_T_8;
14-
wire [63:0] _rotateInput_T_12 = 4'h6 == io_dir ? 64'h0 : _rotateInput_T_10;
12+
wire [63:0] _rotateInput_T_8 = 5'ha == io_dir ? _rotateInput_T_3 : 64'h0;
13+
wire [63:0] _rotateInput_T_10 = 5'h8 == io_dir ? io_data : _rotateInput_T_8;
14+
wire [63:0] _rotateInput_T_12 = 5'h9 == io_dir ? 64'h0 : _rotateInput_T_10;
1515
wire [63:0] _rotateInput_T_14 = _rotate_T ? 64'h0 : io_data;
1616
wire [127:0] rotateInput = {_rotateInput_T_12,_rotateInput_T_14};
1717
wire [127:0] _io_out_T = rotateInput >> rotate;

‎flow/designs/src/mock-alu/MockAlu.v‎

Lines changed: 67 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,100 +1,107 @@
11
module MockAlu(
22
input clock,
33
input reset,
4-
input [3:0] io_op,
4+
input [4:0] io_op,
55
input [63:0] io_a,
66
input [63:0] io_b,
77
output [63:0] io_out
88
);
99
wire [63:0] barrel_io_data;
1010
wire [5:0] barrel_io_shiftAmount;
11-
wire [3:0] barrel_io_dir;
11+
wire [4:0] barrel_io_dir;
1212
wire [63:0] barrel_io_out;
13-
wire [63:0] mult_a;
14-
wire [63:0] mult_b;
15-
wire [127:0] mult_o;
16-
wire mult_clk;
17-
wire mult_rst;
18-
wire [63:0] io_out_operand_io_a;
19-
wire [63:0] io_out_operand_io_b;
20-
wire [63:0] io_out_operand_io_out;
21-
wire [63:0] io_out_operand_1_io_a;
22-
wire [63:0] io_out_operand_1_io_b;
23-
wire [63:0] io_out_operand_1_io_out;
24-
wire [63:0] io_out_operand_2_io_a;
25-
wire [63:0] io_out_operand_2_io_b;
26-
wire [63:0] io_out_operand_2_io_out;
27-
reg [3:0] op;
13+
wire [63:0] multResult_mult_a;
14+
wire [63:0] multResult_mult_b;
15+
wire [127:0] multResult_mult_o;
16+
wire multResult_mult_clk;
17+
wire multResult_mult_rst;
18+
wire [63:0] operand_io_a;
19+
wire [63:0] operand_io_b;
20+
wire [63:0] operand_io_out;
21+
wire [63:0] operand_1_io_a;
22+
wire [63:0] operand_1_io_b;
23+
wire [63:0] operand_1_io_out;
24+
wire [63:0] operand_2_io_a;
25+
wire [63:0] operand_2_io_b;
26+
wire [63:0] operand_2_io_out;
27+
reg [4:0] op;
2828
reg [63:0] a;
2929
reg [63:0] b;
30-
wire isSubtraction = op == 4'h1 | op == 4'h8 | op == 4'h9 | op == 4'ha | op == 4'hc | op == 4'hb | op == 4'hd;
30+
wire _isSubtraction_T = op == 5'h4;
31+
wire _isSubtraction_T_1 = op == 5'hb;
32+
wire _isSubtraction_T_2 = op == 5'hc;
33+
wire _isSubtraction_T_3 = op == 5'hd;
34+
wire _isSubtraction_T_4 = op == 5'hf;
35+
wire _isSubtraction_T_5 = op == 5'he;
36+
wire _isSubtraction_T_6 = op == 5'h10;
37+
wire isSubtraction = _isSubtraction_T | _isSubtraction_T_1 | _isSubtraction_T_2 | _isSubtraction_T_3 |
38+
_isSubtraction_T_4 | _isSubtraction_T_5 | _isSubtraction_T_6;
3139
wire [63:0] _modifiedB_T = ~b;
3240
wire [63:0] modifiedB = isSubtraction ? _modifiedB_T : b;
3341
wire [64:0] _extendedResult_T = a + modifiedB;
3442
wire [64:0] _GEN_0 = {{64'd0}, isSubtraction};
35-
wire [65:0] _extendedResult_T_1 = _extendedResult_T + _GEN_0;
36-
wire [64:0] extendedResult = _extendedResult_T_1[64:0];
43+
wire [64:0] extendedResult = _extendedResult_T + _GEN_0;
3744
wire [63:0] result = extendedResult[63:0];
3845
wire carryOut = extendedResult[64];
3946
wire isTrueZero = ~(|result);
4047
wire isNegative = result[63];
41-
wire _io_out_T_1 = ~isTrueZero;
42-
wire _io_out_T_2 = isTrueZero | isNegative;
43-
wire _io_out_T_3 = ~carryOut;
44-
wire _io_out_T_5 = isTrueZero | _io_out_T_3;
45-
wire [63:0] _io_out_T_22 = 4'h2 == op ? io_out_operand_io_out : 64'h0;
46-
wire [63:0] _io_out_T_24 = 4'h3 == op ? io_out_operand_1_io_out : _io_out_T_22;
47-
wire [63:0] _io_out_T_26 = 4'h4 == op ? io_out_operand_2_io_out : _io_out_T_24;
48-
wire [63:0] _io_out_T_28 = 4'h0 == op ? result : _io_out_T_26;
49-
wire [63:0] _io_out_T_30 = 4'h1 == op ? result : _io_out_T_28;
50-
wire [63:0] _io_out_T_32 = 4'h8 == op ? {{63'd0}, isTrueZero} : _io_out_T_30;
51-
wire [63:0] _io_out_T_34 = 4'h9 == op ? {{63'd0}, _io_out_T_1} : _io_out_T_32;
52-
wire [63:0] _io_out_T_36 = 4'ha == op ? {{63'd0}, isNegative} : _io_out_T_34;
53-
wire [63:0] _io_out_T_38 = 4'hc == op ? {{63'd0}, _io_out_T_2} : _io_out_T_36;
54-
wire [63:0] _io_out_T_40 = 4'hb == op ? {{63'd0}, _io_out_T_3} : _io_out_T_38;
55-
wire [63:0] _io_out_T_42 = 4'hd == op ? {{63'd0}, _io_out_T_5} : _io_out_T_40;
56-
wire [63:0] _io_out_T_44 = 4'h5 == op ? barrel_io_out : _io_out_T_42;
57-
wire [63:0] _io_out_T_46 = 4'h6 == op ? barrel_io_out : _io_out_T_44;
58-
wire [63:0] _io_out_T_48 = 4'h7 == op ? barrel_io_out : _io_out_T_46;
48+
wire _T_3 = ~isTrueZero;
49+
wire _T_4 = isTrueZero | isNegative;
50+
wire _T_5 = ~carryOut;
51+
wire _T_7 = isTrueZero | _T_5;
52+
wire [63:0] _io_out_T_2 = 5'h5 == op ? operand_io_out : 64'h0;
53+
wire [63:0] _io_out_T_4 = 5'h6 == op ? operand_1_io_out : _io_out_T_2;
54+
wire [63:0] _io_out_T_6 = 5'h7 == op ? operand_2_io_out : _io_out_T_4;
55+
wire [63:0] _io_out_T_8 = 5'h0 == op ? result : _io_out_T_6;
56+
wire [63:0] _io_out_T_10 = 5'h4 == op ? result : _io_out_T_8;
57+
wire [63:0] _io_out_T_12 = 5'hb == op ? {{63'd0}, isTrueZero} : _io_out_T_10;
58+
wire [63:0] _io_out_T_14 = 5'hc == op ? {{63'd0}, _T_3} : _io_out_T_12;
59+
wire [63:0] _io_out_T_16 = 5'hd == op ? {{63'd0}, isNegative} : _io_out_T_14;
60+
wire [63:0] _io_out_T_18 = 5'hf == op ? {{63'd0}, _T_4} : _io_out_T_16;
61+
wire [63:0] _io_out_T_20 = 5'he == op ? {{63'd0}, _T_5} : _io_out_T_18;
62+
wire [63:0] _io_out_T_22 = 5'h10 == op ? {{63'd0}, _T_7} : _io_out_T_20;
63+
wire [63:0] _io_out_T_24 = 5'h8 == op ? barrel_io_out : _io_out_T_22;
64+
wire [63:0] _io_out_T_26 = 5'h9 == op ? barrel_io_out : _io_out_T_24;
65+
wire [63:0] _io_out_T_28 = 5'ha == op ? barrel_io_out : _io_out_T_26;
5966
reg [127:0] io_out_REG;
6067
BarrelShifter barrel (
6168
.io_data(barrel_io_data),
6269
.io_shiftAmount(barrel_io_shiftAmount),
6370
.io_dir(barrel_io_dir),
6471
.io_out(barrel_io_out)
6572
);
66-
multiplier mult (
67-
.a(mult_a),
68-
.b(mult_b),
69-
.o(mult_o),
70-
.clk(mult_clk),
71-
.rst(mult_rst)
73+
multiplier multResult_mult (
74+
.a(multResult_mult_a),
75+
.b(multResult_mult_b),
76+
.o(multResult_mult_o),
77+
.clk(multResult_mult_clk),
78+
.rst(multResult_mult_rst)
7279
);
73-
assign io_out_operand_io_out = io_out_operand_io_a & io_out_operand_io_b;
74-
assign io_out_operand_1_io_out = io_out_operand_1_io_a | io_out_operand_1_io_b;
75-
assign io_out_operand_2_io_out = io_out_operand_2_io_a ^ io_out_operand_2_io_b;
80+
assign operand_io_out = operand_io_a & operand_io_b;
81+
assign operand_1_io_out = operand_1_io_a | operand_1_io_b;
82+
assign operand_2_io_out = operand_2_io_a ^ operand_2_io_b;
7683
assign io_out = io_out_REG[63:0];
7784
assign barrel_io_data = a;
7885
assign barrel_io_shiftAmount = b[5:0];
7986
assign barrel_io_dir = io_op;
80-
assign mult_a = a;
81-
assign mult_b = b;
82-
assign mult_clk = clock;
83-
assign mult_rst = reset;
84-
assign io_out_operand_io_a = a;
85-
assign io_out_operand_io_b = b;
86-
assign io_out_operand_1_io_a = a;
87-
assign io_out_operand_1_io_b = b;
88-
assign io_out_operand_2_io_a = a;
89-
assign io_out_operand_2_io_b = b;
87+
assign multResult_mult_a = a;
88+
assign multResult_mult_b = b;
89+
assign multResult_mult_clk = clock;
90+
assign multResult_mult_rst = reset;
91+
assign operand_io_a = a;
92+
assign operand_io_b = b;
93+
assign operand_1_io_a = a;
94+
assign operand_1_io_b = b;
95+
assign operand_2_io_a = a;
96+
assign operand_2_io_b = b;
9097
always @(posedge clock) begin
9198
op <= io_op;
9299
a <= io_a;
93100
b <= io_b;
94-
if (4'he == op) begin
95-
io_out_REG <= mult_o;
101+
if (5'h11 == op) begin
102+
io_out_REG <= multResult_mult_o;
96103
end else begin
97-
io_out_REG <= {{64'd0}, _io_out_T_48};
104+
io_out_REG <= {{64'd0}, _io_out_T_28};
98105
end
99106
end
100107
endmodule

flow/designs/src/mock-alu/multiplier.v renamed to flow/designs/src/mock-alu/mult_hancarlson.v

File renamed without changes.

‎flow/designs/src/mock-alu/plot-area-min-clock-period.py‎

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,135 @@
1+
import subprocess
2+
import os
3+
import re
4+
from matplotlib import pyplot as plt
5+
import numpy as np
6+
from matplotlib import cm
7+
import itertools
8+
9+
10+
def run():
11+
test_design = "make DESIGN_CONFIG=designs/asap7/mock-alu/config.mk"
12+
13+
values = {}
14+
15+
# measure three variables at the time.
16+
measurements = {
17+
# "datawidth": (("MOCK_ALU_WIDTH",), (8, 16, 32, 64)),
18+
"operations": (
19+
("MOCK_ALU_OPERATIONS",),
20+
(
21+
"MAC_BRENTKUNG",
22+
"MULT_BRENTKUNG",
23+
"MULT_HANCARLSON",
24+
"MULT_INFERRED",
25+
"MULT_KOGGESTONE",
26+
"MULT_RIPPLE"
27+
# "ADD",
28+
# "ADD8",
29+
# "ADD16",
30+
# "ADD32",
31+
# "MUX1,MUX2",
32+
# "MUX1,MUX2,MUX3,MUX4",
33+
# "MUX1,MUX2,MUX3,MUX4,MUX5,MUX6,MUX7,MUX8",
34+
# "ADD",
35+
# "AND,OR,XOR",
36+
# "OR",
37+
# "SHL,SHR,SRA",
38+
# "ADD,SUB,SETCC_EQ,SETCC_NE,SETCC_LT,SETCC_ULT,SETCC_LE,SETCC_ULE",
39+
# "MULT",
40+
# "AND,OR,XOR,SHL,SHR,SRA,ADD,SUB,SETCC_EQ,SETCC_NE,SETCC_LT,SETCC_ULT,SETCC_LE,SETCC_ULE",
41+
# "AND,OR,XOR,SHL,SHR,SRA,ADD,SUB,SETCC_EQ,SETCC_NE,SETCC_LT,SETCC_ULT,SETCC_LE,SETCC_ULE,MULT",
42+
),
43+
),
44+
}
45+
measure_ids = sorted(measurements.keys())
46+
47+
for measurement in itertools.product(
48+
*map(lambda key: measurements[key][1], measure_ids)
49+
):
50+
variant = "-".join(map(str, measurement)).replace(" ", "-")
51+
print(f"testing {variant}")
52+
env_change = {"FLOW_VARIANT": variant}
53+
for e in itertools.chain(
54+
*map(
55+
lambda measure: map(
56+
lambda var: {var: measure[1]}, measurements[measure[0]][0]
57+
),
58+
zip(measure_ids, measurement),
59+
)
60+
):
61+
u = dict(map(lambda item: (item[0], str(item[1])), e.items()))
62+
env_change.update(u)
63+
env = os.environ.copy()
64+
env.update(env_change)
65+
66+
if not os.path.exists(f"results/asap7/mock-alu/{variant}/5_route.odb"):
67+
print(f"Measuring {variant}")
68+
for cmd in (
69+
test_design + " verilog",
70+
test_design + " route",
71+
):
72+
returncode = subprocess.call(cmd, env=env, shell=True)
73+
if returncode != 0:
74+
print("Skipping variant, doesn't compile: " + variant)
75+
input_string = "report_design_area\nreport_clock_min_period\n"
76+
result = subprocess.check_output(
77+
test_design + " open_route",
78+
shell=True,
79+
env=env,
80+
input=input_string,
81+
text=True,
82+
)
83+
84+
m = re.search(r"period_min\s*=\s*(\d+\.\d+)", result)
85+
if m:
86+
min_period = float(m.group(1))
87+
if m is None:
88+
print("Variant skipped: " + variant)
89+
continue
90+
m = re.search(r"Design area (\d+) u.*", result)
91+
if m:
92+
design_area = float(m.group(1))
93+
if m is None:
94+
print("Variant skipped: " + variant)
95+
continue
96+
values[measurement] = [min_period, design_area]
97+
98+
# Splitting the dictionary into x and y coordinates, and labels
99+
x_coords = [value[0] for value in values.values()]
100+
y_coords = [value[1] for value in values.values()]
101+
labels = list(values.keys())
102+
103+
# Creating the scatter plot
104+
plt.scatter(x_coords, y_coords, color="red")
105+
106+
def custom_wrap(text, max_len=30):
107+
line, length = "", 0
108+
109+
for part in text.split(","):
110+
if length + len(part) > max_len:
111+
yield line
112+
line, length = part, len(part)
113+
else:
114+
line = f"{line},{part}" if line else part
115+
length += len(part) + 1
116+
117+
yield line
118+
119+
# Annotating each point with its label
120+
for i, label in enumerate(labels):
121+
plt.annotate("\n".join(custom_wrap(label[0])), (x_coords[i], y_coords[i]))
122+
123+
# Displaying the plot
124+
plt.xlabel("minimum period/ps")
125+
plt.ylabel("area/u^2")
126+
plt.title("ALU Operations and minimum period and area")
127+
plt.grid(True)
128+
129+
# plt.gca().invert_xaxis()
130+
# plt.gca().invert_yaxis()
131+
plt.show()
132+
133+
134+
if __name__ == "__main__":
135+
run()

‎flow/designs/src/mock-alu/src/main/resources/README.md‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
Multiplier algorithms
2+
=====================
3+
4+
The multiplier is implemented in ASAP7 using Perhaps https://github.com/antonblanchard/vlsiffra
5+
6+
7+
multiply-hancarlson.v is generated with:
8+
9+
vlsi-multiplier --bits=64 --algorithm=hancarlson --tech=asap7 --register-post-ppa --register-post-ppg --output=multiply-hancarlson.v

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